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參數資料
型號: ATT3042-70S44I
廠商: Electronic Theatre Controls, Inc.
元件分類: FPGA
英文描述: Field-Programmable Gate Arrays
中文描述: 現場可編程門陣列
文件頁數: 63/80頁
文件大小: 528K
代理商: ATT3042-70S44I
Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Lucent Technologies Inc.
63
Electrical Characteristics
(continued)
Figure 36. Master Serial Mode Switching Characteristics
Table 26. Master Serial Mode Switching Characteristics
Notes:
At powerup, V
CC
must rise from 2.0 V to V
CC
minimum in less than 25 ms. If this is not possible, configuration can be delayed by
holding
RESET
low until V
CC
has reached 4.0 V. A very long V
CC
rise time of >100 ms, or a nonmonotonically rising V
CC
may require
a >1 μs high level on
RESET
, followed by >6 μs low level on
RESET
and D/
P
after V
CC
has reached 4.0 V.
Configuration can be controlled by holding
RESET
low with or until after the
INIT
of all daisy-chain slave mode devices is high.
Master serial mode timing is based on slave mode testing.
Signal
Description
Symbol
Min
Max
Unit
CCLK
Data-in Setup
Data-in Hold
1
2
T
DSCK
T
CKDS
60
0
ns
ns
T
DSCK
T
CKDS
CCLK
(OUTPUT)
SERIAL DIN
SERIAL DOUT
(OUTPUT)
1
2
5-3127(F).a
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