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參數(shù)資料
| 型號： | ATT3042-70T84I |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 1/80頁 |
| 文件大小： | 528K |
| 代理商： | ATT3042-70T84I |
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Data Sheet
February 1997
ATT3000 Series Field-Programmable Gate Arrays
Features
I
High performance:
— Up to 270 MHz toggle rates
— 4-input LUT delays <2.7 ns
I
User-programmable gate arrays
— Unlimited reprogrammability
— Easy design iteration through in-system
logic changes
I
Flexible array architecture:
— Compatible arrays ranging from 1500 to
6000 gate logic complexity
— Extensive register, combinatorial, and I/O
capabilities
— Low-skew clock nets
— High fan-out signal distribution
— Internal 3-state bus capabilities
— TTL or CMOS input thresholds
— On-chip oscillator amplifier
I
Standard product availability:
— Low-power 0.55 μm CMOS, static memory
technology
— Pin-for-pin compatible with
Xilinx*
XC3000*
and
XC3100*
families
— Cost-effective for volume production
— 100% factory pretested
— Selectable configuration modes
I
ORCA
Foundry for ATT3000
Development
System support
I
All FPGAs processed on a QML-certified line
I
Extensive packaging options
Description
The CMOS ATT3000 Series Field-Programmable
Gate Array (FPGA) family provides a group of high-
density, digital integrated circuits. Their regular,
extendable, flexible, user-programmable array
architecture is composed of a configuration program
store plus three types of configurable elements: a
perimeter of I/O blocks, a core array of logic blocks,
and resources for interconnection. The general struc-
ture of an FPGA is shown in Figure 1.
The
ORCA
Foundry for ATT3000 Development Sys-
tem provides automatic place and route of netlists.
Logic and timing simulation are available as design
verification alternatives. The design editor is used for
interactive design optimization and to compile the
data pattern that represents the configuration pro-
gram.
The FPGA’s user-logic functions and interconnec-
tions are determined by the configuration program
data stored in internal static memory cells. The pro-
gram can be loaded in any of several modes to
accommodate various system requirements. The
program data resides externally in an EEPROM,
EPROM, or ROM on the application circuit board, or
on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of pro-
gram data at powerup. A serial configuration PROM
can provide a very simple serial configuration pro-
gram storage.
*
Xilinx
,
XC3000,
and
XC3100
are registered trademarks of
Xilinx, Inc.
Table 1. ATT3000 Series FPGAs
FPGA
Max
Logic
Gates
1,500
2,000
3,000
4,500
6,000
Typical Gate
Range
Configurable
Logic
Blocks
64
100
144
224
320
Array
User I/Os
Max
Flip-
Flops
Horizontal
Long Lines
Configuration
Data Bits
ATT3020
ATT3030
ATT3042
ATT3064
ATT3090
1,000—1,500
1,500—2,000
2,000—3,000
3,500—4,500
5,000—6,000
8 x 8
10 x 10
12 x 12
16 x 14
20 x 16
64
80
96
120
144
256
360
480
688
928
16
20
24
32
40
14,779
22,176
30,784
46,064
64,160
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| ATT3064 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3064-100H132I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3064-100H44I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3064-100H68I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
| ATT3064-100H84I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays |
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