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參數資料
| 型號： | AX88178 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller |
| 中文描述： | USB接口10/100/1000千兆以太網/電話線網絡控制器 |
| 文件頁數： | 11/35頁 |
| 文件大小： | 218K |
| 代理商： | AX88178 |
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ASIX ELECTRONICS CORPORATION
11
AX88178 L
USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller
4.1.4 Phy Register Offset for Interrupt Endpoint (0Fh)
Bit 15
Bit 14
Bit 13
Reserved
Bit 7
Bit 6
Bit 5
Reserved
Phy Register Offset 1: Fill in Phy’s Register Offset of Primary Phy here. Upon each Interrupt Endpoint issued, its
register value will be reported in byte# 5 and 6 of Interrupt Endpoint packet.
Phy Register Offset 2: Fill in Phy’s Register Offset of Primary Phy here. Upon each Interrupt Endpoint issued, its
register value will be reported in byte# 7 and 8 of Interrupt Endpoint packet.
4.1.5 Max Packet Size High/Low Byte (10h)
Fill in this field the maximum RX/TX MAC frame size supported by this ASIC when Jumbo Frame mode is disabled. The
number must be even number in terms of byte and should be less than or equal to 2500 bytes. When Jumbo Frame mode
is enabled, the maximum MAC frame size is fixed to 9216 bytes and this setting is ignored.
4.1.6 Primary/Secondary Phy_Type and Phy_ID (11h)
The 3 bits Phy_Type field for both Primary and Secondary Phy is defined as follows,
3’b000: 10/100 Ethernet Phy or 1M HOME Phy (Link reports as normal case).
3’b100: Special case 1 (Link reports as always active).
3’b001: Gigabit Ethernet Phy.
3’b111: non-supported Phy. For example, the High Byte value of “E0h” in EEPROM offset of “11h” means that
secondary Phy is not supported.
4.1.7 Pause Frame High Water and Low Water Mark (12H)
When operating in full-duplex mode, correct setting of this field is very important and can affect the overall packet
receive throughput performance in a great deal. The High Water Mark is the threshold to trigger sending of Pause frame
and the Low Water Mark is the threshold to stop sending of Pause frame. Note that each free buffer count here represents
256 bytes of packet storage space in SRAM.
When Jumbo frame mode is not disabled, user can fill in a smaller value in High Water Mark and a larger value in Low
Water Mark fields to have more efficient use of SRAM for packet buffering.
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Phy Register Offset 1
Bit 3
Bit 2
Phy Register Offset 2
Bit 4
Bit 1
Bit 0
Total free buffer count = 80
Start sending Pause frame when free buffer < High Water Mark
0
Stop sending Pause frame when free buffer > Low Water Mark
相關PDF資料 |
PDF描述 |
|---|---|
| AX88178L | USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller |
| AY-5-8116 | DUAL BAUD RATE GENERATOR |
| AY-5-8116T | DUAL BAUD RATE GENERATOR |
| AY-5-8136 | DUAL BAUD RATE GENERATOR |
| AY-5-8136T | DUAL BAUD RATE GENERATOR |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AX88178A | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88179 -- USB3.0 轉 10/100/1000M 千兆以太網控制芯片 |
| AX88178L | 制造商:ASIX 制造商全稱:ASIX 功能描述:USB to 10/100/1000 Gigabit Ethernet/HomePNA Controller |
| AX88179 | 制造商:ASIX 制造商全稱:ASIX 功能描述:AX88179 -- USB3.0 轉 10/100/1000M 千兆以太網控制芯片 |
| AX88179QF | 制造商:ASIX Electronics Corporation 功能描述: |
| AX88180 | 制造商:ASIX 制造商全稱:ASIX 功能描述:High-Performance Non-PCI 32-bit 10/100/1000M Gigabit Ethernet Controller |
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