參數資料
| 型號： | BBT3420-SN |
| 廠商： | Intersil |
| 文件頁數： | 1/38頁 |
| 文件大小： | 0K |
| 描述： | TXRX QUAD MULTI-RATE 289-EBGA |
| 標準包裝： | 84 |
| 類型： | 收發器 |
| 驅動器/接收器數： | 4/4 |
| 規程： | XAUI，XGMII，MDC/MDIO |
| 電源電壓： | 1.7 V ~ 1.9 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 289-BGA |
| 供應商設備封裝： | 289-BGA（19x19） |
| 包裝： | 托盤 |
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1
FN7481.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774
| Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2004, 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
BBT3420
Quad 2.488-3.1875Gbps/Channel Transceiver
1 Features
Four channels of transmitter and receiver with serial data
transfer rates of 2.488-3.1875Gbps/channel with full rate
and half-rate operations
Up to 12.75Gbps data rate at full duplex
User-controlled dual-speed operation (per channel) 2.488-
3.1875Gbps or 1.244-1.59Gbps
IEEE 802.3ae-2002 10 GE and 10 GFC compliant
- XAUI, XGMII, and MDC/MDIO interfaces
XGMII format 10-bit parallel input/output data
- Supports HSTL 1.8V and 2.5V SSTL_2
Extensive configuration via 802.3-compliant MDC/MDIO
serial interface
8bit/10bit Encoding/Decoding per channel with selectable
parallel input/output data sizes
- Support optional 8b/10b encoder/decoder bypass
operation
Integrated Equalization and Pre-emphasis
De-skewing and channel-to-channel alignment options
Low power, 250mW per channel typical
Meets jitter requirements with significant margin
Comma detection and synchronization, byte alignment
Tx/Rx rate matching via IDLE insertion/deletion
Receive signal detect and 16 levels of transmission
medium equalization
CML transmit outputs with four levels of pre-emphasis
Loopback
- Per-channel serial Tx-to-Rx and Rx-to-Tx parallel
internal loopback modes
Single-ended/differential input Reference clock
Double Data-Rate (DDR) mode, also optional SDR (Single
Data Rate) on transmitter
Support both source-centered and source-simultaneous
clocking
Long Run Length (512 bit) frequency lock ideal for
proprietary encoding schemes Transmit byte clock
schemes
- One Transmit Byte Clock (TBC) for each channel, or
one TBC for all four channels
Received clock schemes
- Receive data aligned to local reference clock, to
recovered clock for each channel, or to recovered clock
for Channel A only
Supports Built-In Self Test (BIST) and IEEE 1149.1 JTAG
On-chip 25
series output terminations (XGMII side)
Standard 0.18m 1.8V CMOS technology
3.3V tolerant I/O
FIGURE 1-1. EXAMPLE BACKPLANE AND LINE CARD APPLICATIONS
Switch Card
Switch
Fabric
nPower BBT 3420
Transceiver
nPower BBT 3420
Transceiver
nPower BBT 3420
Transceiver
Serial 10 Gigabit
10GBASE-R
Custom ASIC
&
MAC Functions
XGMII
nPower BBT 3420
Transceiver
XAUI
XAUI
XGMII
XAUI
Up to 40"
Optical
Transponder
nPower BBT 3420
Transceiver
WDM 10 Gigabit
10GBASE-LX4
Custom ASIC
&
MAC Functions
XGMII
nPower BBT 3420
Transceiver
XAUI
XAUI
XGMII
XAUI
Up to 40"
WDM
Optical
Transponder
B
ackp
lan
e
In
ter
face
Data Sheet
September 14, 2005
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