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參數資料
| 型號： | bq2202 |
| 廠商： | Benchmark Technology Group |
| 英文描述： | SRAM Nonvolatile Controller With Reset(靜態RAM非易失性控制器單元(帶復位）) |
| 中文描述： | 非易失控制器的SRAM（靜態RAM的非易失性控制器單元（帶復位）帶復位） |
| 文件頁數： | 1/10頁 |
| 文件大小： | 83K |
| 代理商： | BQ2202 |
Features
Power monitoring and switching
for nonvolatilecontrol of SRAMs
Write-protect control
Input decoder allows control of
up to2 banks of SRAM
3-volt primary cell input
3-volt rechargeable battery in-
put/output
Reset output for system power-on
reset
L ess than 10ns chip enable
propagation delay
5% or 10% supply operation
General Description
The CMOS bq2202 SRAM Nonvolatile
Controller With Reset provides all the
necessary functions for converting one
or two banks of standard CMOS
SRAM into nonvolatile read/write
memory.
A precision comparator monitors the
5V V
CC
input for an out-of-tolerance
condition. When out-of-tolerance is
detected, the two conditioned
chip-enable outputs are forced inac-
tive to write-protect both banks of
SRAM.
Power for the external SRAMs is
switched from the V
CC
supply to the
battery-backup supply as V
CC
de-
cays. On a subsequent power--up, the
V
OU T
supply is automatically
switched from the backup supply to
the V
CC
supply. The external SRAMs
are write-protected until a power-
valid condition exists. The reset out-
put provides power-fail and power-on
resets for thesystem.
During power-valid operation, the
input decoder selects one of two
banks of SRAM.
1
Pin Names
V
OUT
RST
THS
CE
CE
CON1
,
CE
CON2
A
BC
P
BC
S
NC
V
CC
V
SS
Supply output
Reset output
Threshold select input
Chip enable active low input
Conditioned chip enable outputs
Bank select input
3V backup supply input
3V rechargeable backup supply input/output
No connect
+5 volt supply input
Ground
Two banks of CMOS static RAM can be battery-backed
using the V
OUT
and conditioned chip-enable output pins
from the bq2202. As the voltage input V
CC
slews down
during a power failure, the two conditioned chip enable
outputs, CE
CON1
and CE
CON2
, are forced inactive
independent of thechip enableinput CE.
This activity unconditionally write-protects external
SRAM as V
CC
falls to an out-of-tolerance threshold
V
PFD
. V
PFD
is selected by the threshold select input pin,
THS. If THS is tied to V
SS
, the power-fail detection oc-
curs at 4.62V typical for 5% supply operation.
If THS is tied to V
CC
, power-fail detection occurs at
4.37V typical for 10% supply operation. The THS pin
must betied toV
SS
or V
CC
for proper operation.
If a memory access is in process to any of the two exter-
nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t
WPT
(150
μ
sec maximum), the two chip en-
able outputs are unconditionally driven high, write-
protecting thecontrolled SRAMs.
SRAM NV Controller With Reset
bq2202
Sept. 1997 D
1
PN220201.eps
16-Pin Narrow DIP or SOIC
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
BCS
CE
CECON1
CECON2
NC
RST
NC
VOUT
BCP
NC
A
NC
NC
THS
VSS
Functional Description
Pin Connections
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相關代理商/技術參數 |
參數描述 |
|---|---|
| BQ2202PN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SRAM NV Controller With Reset |
| BQ2202PNN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SRAM NV Controller With Reset |
| BQ2202PN-N | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| BQ2202SN | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| BQ2202SNN | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SRAM NV Controller With Reset |
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