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參數資料
| 型號： | BT497KHF135 |
| 廠商： | BROOKTREE CORP |
| 元件分類： | 顯示控制器 |
| 英文描述： | 1600 X 1280 PIXELS PALETTE-DAC DSPL CTLR, PQFP160 |
| 文件頁數： | 1/122頁 |
| 文件大小： | 986K |
| 代理商： | BT497KHF135 |
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Brooktree
Brooktree Corporation 9868 Scranton Road San Diego, CA 92121-3707 619-452-7580
1-800-2-BT-APPS FAX: 619-452-1249 Internet: apps@brooktree.com L497001 Rev. B
Bt498
Bt497
Distinguishing Features
PLL pixel clock generation (M/N)
Supports true-color 1600 x 1280
resolutions
Up to 128-bit input pixel port width
220 and 135 MHz operation
Multiple display modes on a pixel
basis
High-resolution true-color support
2:1 and 4:1 multiplexed pixel port
support
Programmable pixel format
Three 256 x 8 color palette RAMs
Three 256 x 8 gamma LUT ROMs
(
γ = 2.2)
64 x 64 x 2 programmable cursor
Programmable setup (0 or 7.5 IRE)
VRAM shift clock generation
On-chip user-denable video
timing generator
JTAG support
160-pin (Bt497), 208-pin (Bt498)
PQFP packages
LVTTL (3.3 V) I/O interface
Applications
High-resolution color 3D graphics
CAE/CAD/CAM
Image processing
Instrumentation
Desktop publishing
The Bt497/8 is designed specically for high-performance, high-resolution color
graphics applications. The architecture enables the display of true-color 1600 x 1280
bit-mapped color graphics at 76 Hz refresh rates. The wide input pixel port and inter-
nal multiplexing modes enable TTL-compatible interfacing to the frame buffer,
while maintaining PLL-generated 220 MHz, or externally provided 220 MHz video
data rates required for high-refresh-rate, high-resolution color graphics.
The Bt497/8 supports PLL pixel clock generation, supporting a variety of fre-
quencies using an M/N divisor scheme. This decreases system cost due to the elimi-
nation of multiple crystal oscillators that are used to support a variety of monitor and
refresh rates.
The Bt497/8 contains three 256 x 8 color lookup tables, three 256 x 8 gamma
ROM (
γ = 2.2), triple 8-bit video D/A converters, a programmable 64 x 64 x 2 cur-
sor, and a fully programmable video timing generator.
The Bt497/8 RAMDAC allows different display modes of operation for each
pixel. Utilizing a window-type scheme, each set of pixel and control bits maps the
accompanying pixel data to a user-dened display mode. The window identication
index addresses a color model table which determines the description of the pixel
data. For example, separate windows displaying 24-plane true color, 8-plane pseudo-
color, and 24-plane double-buffer true color can exist within a single frame.
A programmable setup (0 or 7.5 IRE) is included.
Functional Block Diagram
CLOCK
CLOCK*
LD
SC*
P[127:0]
STSCAN
FIELD
CSYNC*
SCEN*
Pixel Port
Registers
Clock
MPX
Pixel
Clock
PLL
64 x 64 x 2
Cursor RAM
Bus Control
CE* R/W C[1,0] LB*
D[7:0]
Data Bus Mux
IOB
IOG
IOR
COMP
COMP2
Pixel
Unpacking
Logic
VAA GND
RANGE
XTAL[1] XTAL[2]
VREF
FSADJ
256 x 8 RAM
256 x 8 Gamma ROM
3 x 8 Cursor LUT
256 x 8 RAM
256 x 8 Gamma ROM
3 x 8 Cursor LUT
256 x 8 RAM
256 x 8 Gamma ROM
3 x 8 Cursor LUT
Pixel Load
Control
Video Timing
Generator
JT
AG
TDO
TDI
TCK
TMS
220 MHz Monolithic
CMOS Triple 256 x 8 RAMDAC
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