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參數(shù)資料
| 型號： | BU-61581S2-200 |
| 英文描述： | MIL-STD-1553/ARINC Bus Controller/RTU |
| 中文描述： | MIL-STD-1553/ARINC總線控制器/ RTU通訊 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大小： | 833K |
| 代理商： | BU-61581S2-200 |
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Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7234
FEATURES
Complete Integrated 1553B Notice 2
Interface Terminal
Direct Replacement for BUS-61559
AIM-HY’er Series
Functional Superset of BUS-61553
AlM-HY Series
Internal Address and Data Buffers for
Direct Interface to Processor Bus
RT Subaddress Circular Buffers to
Support Bulk Data Transfers
Optional Separation of RT Broadcast
Data
Internal Interrupt Status and Time Tag
Registers
Internal Command Illegalization
MIL-PRF-38534 Processing Available
Transmitter Inhibit Control for
Individual Bus Channels
DESCRIPTION
DDC’s BU-61559 series of Advanced Integrated Mux Hybrids with
enhanced RT Features (AIM-HY’er) comprise a complete interface
between a microprocessor and a MIL-STD-1553B Notice 2 bus,
implementing Bus Controller (BC), Remote Terminal (RT), and
Monitor Terminal (MT) modes. Packaged in a single 78-pin DIP or flat
package, the BU-61559 series contains dual low-power transceivers
and encoder/decoders, complete BC/RT/MT protocol logic, memory
management and interrupt logic, 8K x 16 of shared static RAM, and
a direct, buffered interface to a host processor bus.
The BU-61559 includes a number of advanced features that support
MIL-STD-1553B Notice 2 and STANAG 3838. Other salient features
of the BU-61559 serve to provide the benefits of reduced board space
requirements, enhanced software flexibility, and reduced host proces-
sor overhead.
The BU-61559 contains internal address latches and bidirectional
data buffers to provide a direct interface to a host processor bus.
Alternatively, the buffers may be operated in a fully transparent mode
in order to interface to up to 64K words of external shared RAM
and/or connect directly to a component set supporting the 20 MHz
STANAG 3910 bus.
The memory management scheme for RT mode provides an option
for separation of broadcast data, in compliance with 1553B Notice 2.
A circular buffer option for RT message data blocks offloads the host
processor for bulk data transfer applications.
The BU-61559 series hybrids operate over the full military tempera-
ture range of -55 to +125°C and MIL-PRF-38534 processing is avail-
able. The hybrids are ideal for demanding military and industrial
microprocessor-to-1553 applications.
2002 Data Device Corporation
BU-61559 SERIES
MIL-STD-1553B NOTICE 2 AIM-HY’ER
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61581S2-300 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581S3-102 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581S3-112 | GHz LGA Sockets; IC Size X (mm): 6; IC Size Y (mm): 4; IC Array X: 11; IC Array Y: 7; Max Pincount: 77; Top Pitch (mm): 0.5; Pad diameter max (mm): 0.3; IC Ball Diameter Max (mm): IC Size Tolerance (mm): 0.1; IC Total Height Max (mm): 1.1; Max Package Code: LGA77; Backing Plate: no; Cavity Down: no; Heat Sink: no; IC Top Surface: Flat; Socket Lid: Swivel; Part Description: Diamond Particle LGA Socket (ZIF); |
| BU-61581V2-200 | MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581V2-300 | MIL-STD-1553/ARINC Bus Controller/RTU |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61581S2-300 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581S3-102 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581S3-112 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581S3-122 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
| BU-61581S6-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553/ARINC Bus Controller/RTU |
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