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參數(shù)資料
| 型號： | BU-61865F4-402 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 X 1 INCH, 0.155 INCH HEIGHT, FP-72 |
| 文件頁數(shù)： | 1/56頁 |
| 文件大小： | 304K |
| 代理商： | BU-61865F4-402 |
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BU-6174X/6184X/6186X
DESCRIPTION
The Enhanced Mini-ACE family of
MIL-STD-1553 terminals provide
complete interfaces between a host
processor and a 1553 bus. These
terminals integrate dual transceiver,
protocol logic, and 4K words or 64K
words of RAM.
With a 1.0 inch square package, the
Enhanced Mini-ACE is nearly 100%
footprint and software compatibile
with the previous generation Mini-
ACE (Plus) terminals, and is soft-
ware compatibile with the older ACE
series.
The Enhanced Mini-ACE is powered
by a choice 5V, or 5V/3.3V (3.3V
logic).
Multiprotocol
support
of
MIL-STD-1553A/B
and
STANAG
3838, including versions incorporat-
ing McAir compatible transmitters, is
provided. There is a choice of 10, 12,
16, or 20 Mhz clocks. The BC/RT/MT
versions with 64K words of RAM
include built-in RAM parity checking.
BC features include a built-in mes-
sage sequence control engine, with
a set of 20 instructions. This provides
an autonomous means of imple-
menting
multi-frame
message
scheduling, message retry schemes,
data double buffering, asynchronous
message insertion, and reporting to
the
host
CPU.
The
Enhanced
Mini-ACE
incorporates
a
fully
autonomous built-in self-test, which
provides comprehensive testing of
the internal protocol logic and/or
RAM.
The Enhanced Mini-ACE RT offers
the same choices of subaddress
buffering as the ACE and Mini-ACE
(Plus), along with a global circular
buffering option, 50% rollover inter-
rupt for circular buffers, an interrupt
status queue, and an "Auto-boot"
option to support MIL-STD-1760.
The Enhanced Mini-ACE terminals
provide the same flexibility in host
interface
configurations
as
the
ACE/Mini-ACE, along with a reduc-
tion in the host processor's worst
case holdoff time.
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
(ENHANCED MINI-ACE)
TRANSCEIVER
A
CH. A
TRANSCEIVER
B
CH. B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
RT ADDRESS
SHARED
RAM
ADDRESS BUS
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
DATA BUS
D15-D0
A15-A0
DATA
BUFFERS
ADDRESS
BUFFERS
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
MISCELLANEOUS
INCMD
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
RTAD4-RTAD0, RTADP
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
TX/RX_A
TX/RX_B
*
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
2000 Data Device Corporation
FIGURE 1. ENHANCED MINI-ACE BLOCK DIAGRAM
FEATURES
FULLY INTEGRATED 1553A/B NOTICE 2,
MCAIR, STANAG 3838 INTERFACE TERMINAL
COMPATIBLE WITH MINI-ACE (PLUS)
AND ACE GENERATIONS
CHOICE OF :
RT OR BC/RT/MT IN SAME FOOTPRINT
RT OR BC/RT/MT WITH 4K RAM
BC/RT/MT WITH 64K RAM, WITH RAM PARITY
CHOICE OF 5V OR 3.3V LOGIC
5V TRANSCEIVER WITH 1760 AND
MCAIR COMPATIBLE OPTIONS
COMPREHENSIVE BUILT-IN SELF-TEST
FLEXIBLE PROCESSOR/MEMORY
INTERFACE, WITH REDUCED HOST WAIT TIME
CHOICE OF 10, 12, 16, OR 20 MHZ CLOCK
HIGHLY AUTONOMOUS BC WITH
BUILT-IN MESSAGE SEQUENCE CONTROL:
FRAME SCHEDULING
BRANCHING
ASYNCHRONOUS MESSAGE INSERTION
GENEERAL PURPOSE QUEUE
USER-DEFINED INTERRUPTS
ADVANCED RT FUNCTIONS
GLOBAL CIRCULAR BUFFERING
INTERRUPT STATUS QUEUE
50% CIRCULAR BUFFER ROLLOVER
INTERRPTS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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