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參數(shù)資料
| 型號： | BU-65142D3-140Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
| 封裝： | 45.70 X 53.30 MM, 5.30 MM HEIGHT, CERAMIC, QIP-78 |
| 文件頁數(shù)： | 1/28頁 |
| 文件大小： | 264K |
| 代理商： | BU-65142D3-140Q |
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BU-65142 series*
The BU-65142 Series is a Hi-Rel
radiation tolerent complete dual
redundant MIL-STD-1553 Remote
Terminal Unit (RTU). The device is
based upon two DDC custom ICs,
which includes two monolithic bi-
polar low power transceivers and
one RiCmos protocol containing
data buffers and timing control logic.
It supports all 13 mode codes for dual
redundant operation, any combina-
tion of which can be illegalized.
Parallel data transfers are accom-
plished with a DMA type handshak-
ing, compatible with most CPU
types. Data transfers to/from mem-
ory are simplified by the latched
command word and word count out-
puts.
Error detection and recovery are
enhanced by BU-65142 Series spe-
cial features. A 14-bit built-in-test
word register stores RTU information,
and sends it to the Bus Controller in
response to the Mode Command
Transmit Bit Word. The BU-65142
Series performs continuous on-line
wraparound self-test, and provides
four error flags to the host CPU.
Inputs are provided for host CPU con-
trol of 6 bits of the RTU Status Word.
Its integrated hermetic package,
-55°C to +125°C operating tempera-
ture range, and complete RTU opera-
tion make the BU-65142 ideal for
MIL-STD-1553 applications requiring
hardware or microprocessor subsys-
tems.
MIL-STD-1553 DUAL REDUNDANT
REMOTE TERMINAL HYBRID
FEATURES
Radiation Tolerant to 300 krad
Complete Integrated Remote
Terminal Including:
–Dual Low-Power Transceivers
–Complete RT Protocol
Multiple Ordering Options;
+5V (Only), +5V/-15V, and +5V/-12V
Direct Interface to Systems With
No Processor
Space Qualified
High Reliability Screening
DATA
BUS A
DATA
BUS B
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
PROTOCOL
SEQUENCER
AND
CONTROL
LOGIC
BUFFER
TRANSFER
CONTROLS
CURRENT
WORD
COUNTER
COMMAND
LATCH
STATUS
REGISTER
ERROR FLAGS
TIMING FLAGS
NBGT
INCMD
BITEN
STATEN
GBR
MESS ERR
RT FAIL
HS FAIL
RTADD ERR
ILL CMD (ME)
SS REQ
ADBC
RT FLAG
SS BUSY
SS FLAG
DAT/CMD
A5-A10
A0-A4
DTREQ
DTGRT
DTACK
DTSTR
R/W
DB0-DB15
BUF ENA
M
U
X
WATCHDOG
TIMEOUT
DDC CUSTOM CHIP
RT ADDRESS
+
PARITY
16 MHz CLOCK
D-RAD
FIGURE 1. BU-65142 SERIES BLOCK DIAGRAM
DESCRIPTION
1988, 1999 Data Device Corporation
*(Note: BU-65142 is NOT recommended for new design, consult factory or local representative for more information)
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| BU-65142D3-280 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQIP78 |
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