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參數(shù)資料
| 型號(hào)： | BU-65145F2-330Y |
| 英文描述： | Phase Locked Loop |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 1/24頁(yè) |
| 文件大小： | 219K |
| 代理商： | BU-65145F2-330Y |
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BU-65142 and BUS-65142 SERIES
The BUS-65142 Series is a com-
plete dual redundant MIL-STD-
1553 Remote Terminal Unit (RTU)
packaged in a small 1.9" x 2.1"
hybrid. The device is based upon
two
DDC
custom
ICs,
which
includes two monolithic bi-polar low
power transceivers and one CMOS
protocol containing data buffers
and timing control logic. It supports
all 13 mode codes for dual redun-
dant operation, any combinaion of
which can be illegalized.
Parallel data transfers are accom-
plished with a DMA type handshak-
ing, compatible with most CPU
types. Data transfers to/from mem-
ory are simplified by the latched
command word and word count out-
puts.
Error detection and recovery are
enhanced by BUS-65142 Series
special features. A 14-bit built-in-
test word register stores RTU infor-
mation, and sends it to the Bus
Controller in response to the Mode
Command Transmit Bit Word. The
BUS-65142 Series performs contin-
uous on-line wraparound self-test,
and provides four error flags to the
host CPU. Inputs are provided for
host CPU control of 6 bits of the
RTU Status Word.
Its small hermetic package, -55°C
to +125°C operating temperature
range, and complete RTU operation
make the BUS-65142 ideal for most
MIL-STD-1553 applications requir-
ing hardware or microprocessor
subsystems.
MIL-STD-1553 DUAL REDUNDANT
REMOTE TERMINAL HYBRID
FEATURES
Complete Intergrated Remote
Terminal Including:
–Dual Low-Power Transceivers
–Complete RT Protocol
Direct Interface to Systems With
No Processor
Radiation Tolerant Version
Available
Space Qualified Version
Available
High Reliability Screening
Available
DATA
BUS A
DATA
BUS B
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
PROTOCOL
SEQUENCER
AND
CONTROL
LOGIC
BUFFER
TRANSFER
CONTROLS
CURRENT
WORD
COUNTER
COMMAND
LATCH
STATUS
REGISTER
ERROR FLAGS
TIMING FLAGS
NBGT
INCMD
BITEN
STATEN
GBR
MESS ERR
RT FAIL
HS FAIL
RTADD ERR
ILL CMD (ME)
SS REQ
ADBC
RT FLAG
SS BUSY
SS FLAG
DAT/CMD
A5-A10
A0-A4
DTREQ
DTGRT
DTACK
DTSTR
R/W
DB0-DB15
BUF ENA
M
U
X
WATCHDOG
TIMEOUT
DDC CUSTOM CHIP
RT ADDRESS
+
PARITY
16 MHz CLOCK
FIGURE 1. BUS-65142 SERIES BLOCK DIAGRAM
DESCRIPTION
1988, 1999 Data Device Corporation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-65145F2-330Z | Phase Locked Loop |
| BU-65145F2-340 | Phase Locked Loop |
| BU-65145F2-340K | Controller Miscellaneous - Datasheet Reference |
| BU-65145F2-340L | Controller Miscellaneous - Datasheet Reference |
| BU-65145F2-340Q | Controller Miscellaneous - Datasheet Reference |
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