欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數資料
型號: BU-65170G0-180Q
廠商: DATA DEVICE CORP
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
封裝: GULLWING PACKAGE-70
文件頁數: 1/44頁
文件大小: 563K
代理商: BU-65170G0-180Q
BU-65170/61580 and BU-61585
DESCRIPTION
DDC's BU-65170, BU-61580 and
BU-61585 Bus Controller / Remote
Terminal
/
Monitor
Terminal
(BC/RT/MT)
A d v anced
Communication Engine (ACE) termi-
nals comprise a complete integrated
interface between a host processor
and a MIL-STD-1553 A and B or
STANAG 3838 bus.
The ACE series is packaged in a 1.9 -
square-inch,
70-pin,
low-profile,
cofired
MultiChip
Module
(MCM)
ceramic package that is well suited for
applications with stringent height
requirements.
The BU-61585 ACE integrates dual
transceiver, protocol, memory man-
agement, processor interface logic,
and a total of 12K words of RAM in a
choice of DIP or flat pack packages.
The BU-61585 requires +5 V power
and either -15 V or -12 V power.
The BU-61585 internal RAM can be
configured as 12K x 16 or 8K x 17.
The 8K x 17 RAM feature provides
capability for memory integrity check-
ing by implementing RAM parity gen-
eration and verification on all access-
es. To minimize board space and
“glue” logic, the ACE provides ultimate
flexibility in interfacing to a host
processor and internal/external RAM.
The advanced functional architecture
of the ACE terminals provides soft-
ware
compatibility
to
DDC's
Advanced Integrated Multiplexer (AIM)
series hybrids, while incorporating a
multiplicity of architectural enhance-
ments. It allows flexible operation
while off-loading the host processor,
ensuring data sample consistency,
and supports bulk data transfers.
The ACE hybrids may be operated at
either 12 or 16 MHz. Wire bond
options allow for programmable RT
address (hardwired is standard) and
external transmitter inhibit inputs.
MIL-STD-1553A/B NOTICE 2 RT and BC/RT/MT,
ADVANCED COMMUNICATION ENGINE (ACE)
FEATURES
Fully Integrated MIL-STD-1553
Interface Terminal
Flexible Processor/Memory
Interface
Standard 4K x 16 RAM and
Optional 12K x 16 or 8K x 17 RAM
Available
Optional RAM Parity
Generation/Checking
Automatic BC Retries
Programmable BC Gap Times
BC Frame Auto-Repeat
Flexible RT Data Buffering
Programmable Illegalization
Selective Message Monitor
Simultaneous RT/Monitor Mode
TRANSCEIVER
A
CH. A
TRANSCEIVER
B
CH. B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
RT ADDRESS
SHARED
RAM
ADDRESS BUS
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
DATA BUS
D15-D0
A15-A0
DATA
BUFFERS
ADDRESS
BUFFERS
PROCESSOR
DATA BUS
PROCESSOR
ADDRESS BUS
MISCELLANEOUS
INCMD
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
RTAD4-RTAD0, RTADP
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
IOEN, MEMENA-OUT, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
PROCESSOR
AND
MEMORY
CONTROL
INTERRUPT
REQUEST
TX/RX_A
TX/RX_B
*
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
1992, 1999 Data Device Corporation
ACE User’s Guide
Also Available
FIGURE 1. ACE BLOCK DIAGRAM
相關PDF資料
PDF描述
BU-65170G1-180W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
BU-65170G1-190Q 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
BU-65170G2-140L 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
BU-65170G2-140W 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
BU-65170G2-160Y 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CDSO70
相關代理商/技術參數
參數描述
BU65170G0-200 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
BU65170G0-300 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
BU65170G5-100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
BU65170G5-110 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
BU65170G5-120 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Interface IC
主站蜘蛛池模板: 黔东| 巴马| 泰顺县| 宜宾市| 安泽县| 慈利县| 罗平县| 贵州省| 冀州市| 东乡族自治县| 博野县| 三穗县| 高密市| 尉犁县| 庆云县| 固原市| 丹巴县| 汉沽区| 长丰县| 子长县| 阿克陶县| 辽中县| 栖霞市| 福州市| 云梦县| 泌阳县| 鱼台县| 潮安县| 江北区| 石嘴山市| 高尔夫| 西乌珠穆沁旗| 石首市| 大理市| 贵溪市| 三河市| 巴林左旗| 乌拉特前旗| 遂昌县| 榆林市| 泰安市|