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參數資料
| 型號： | BUS-63106-340W |
| 英文描述： | FPGA (Field-Programmable Gate Array) |
| 中文描述： | 總線收發器 |
| 文件頁數： | 1/4頁 |
| 文件大小： | 49K |
| 代理商： | BUS-63106-340W |
DDC’s
BUS-61553
Advanced
Integrated Mux (AIM) Hybrid is a
complete
MIL-STD-1553
Bus
Controller (BC), Remote Terminal
Unit (RTU), and Bus Monitor (MT)
device. Packaged in a single 78-pin
DIP package, the BUS-61553 con-
tains dual low-power transceivers,
complete BC/RT/MT protocol logic, a
MIL-STD-1553-to-host interface unit
and 8K x 16 RAM.
Using an industry standard dual
transceiver and standard status and
control signals, the BUS-61553 sim-
plifies system integration at both the
MIL-STD-1553 and host processor
interface levels.
All 1553 operations are controlled
through the CPU access to the
shared 8K x 16 RAM. To ensure
maximum design flexibility, memory
control lines are provided for attach-
ing external RAM to the BUS-61553
address and data buses and for dis-
abling internal memory; the total
combined memory space can be
expanded to 64K x 16. All 1553 trans-
fers are entirely memory-mapped;
thus the CPU interface requires
minimal hardware and/or software
support.
The BUS-61553 operates over the
full military -55°C to +125°C temper-
ature range. Available screened to
MIL-PRF-38534, the BUS-61553 is
ideal for demanding military and
industrial
microprocessor-to-1553
interface applications.
DESCRIPTION
MIL-STD-1553 ADVANCED INTEGRATED
MUX (AIM) HYBRID
FEATURES
Fully Intergrated Terminal
Including:
–Dual Transceiver
–BC/RT/MT Protocol
–Memory Management Unit
–Processor lnterface Logic
–8K x 16 RAM
CMOS and Bipolar Technologies
Internal Interrupt Status and Time
Tag Registers
High Reliability
883B Processing Available
DATA
BUS A
TRANSFORMER A
BUS-25679
8
4
1
2
3
BUS-25679
DATA
BUS B
TRANSFORMER B
8
4
3
2
1
TX
RX
TRANSCEIVER B
INH
768
s
TIME OUT
TX
RX
INH
TRANSCEIVER A
CHANNEL A
ENCODER/
DECODER
MEMORY
TIMING
PROTOCOL
CONTROLLER
CHANNEL B
ENCODER/
DECODER
8K x 16
SHARED RAM
RAM
PARITY
CHECKER
RT ADDR
RTPARERR
RTAD P
RTAD4
RTAD3
RTAD2
RTAD1
RTAD0
INT
EXTLD
EXTEN
MEM/REG
RD/WR
READYD
STRBD
SELECT
MSTRCLR
CLOCK IN
INTERRUPT
GENERATOR
CPU
TIMING
D15-D00
A15-A00
CONTENTION
RESOLVER
FIGURE 1. BU-61553 BLOCK DIAGRAM
SEE ALSO
USER’S
GUIDE
BUS-61553
1987, 1999 Data Device Corporation
相關PDF資料 |
PDF描述 |
|---|---|
| BUS-63106-340Y | FPGA (Field-Programmable Gate Array) |
| BUS-63106-340Z | IC,FPGA,416-CELL,CMOS,BGA,356PIN,PLASTIC |
| BUS-63106-350 | IC,FPGA,416-CELL,CMOS,BGA,356PIN,PLASTIC |
| BUS-63106-350K | FPGA (Field-Programmable Gate Array) |
| BUS-63106-350L | FPGA (Field-Programmable Gate Array) |
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