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參數(shù)資料
| 型號： | BUS-65143-350Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, QIP78 |
| 封裝： | KOVAR, QIP-78 |
| 文件頁數(shù)： | 1/26頁 |
| 文件大小： | 247K |
| 代理商： | BUS-65143-350Q |
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BU-65142 and BUS-65142 SERIES*
The BUS-65142 Series is a com-
plete dual redundant MIL-STD-
1553 Remote Terminal Unit (RTU).
The device is based upon two DDC
custom ICs, which includes two
monolithic bi-polar low power trans-
ceivers and one CMOS protocol
containing data buffers and timing
control logic. It supports all 13 mode
codes for dual redundant operation,
any combination of which can be ille-
galized.
Parallel data transfers are accom-
plished with a DMA type handshak-
ing, compatible with most CPU
types. Data transfers to/from mem-
ory are simplified by the latched
command word and word count out-
puts.
Error detection and recovery are
enhanced by BUS-65142 Series spe-
cial features. A 14-bit built-in-test
word register stores RTU information,
and sends it to the Bus Controller in
response to the Mode Command
Transmit Bit Word. The BUS-65142
Series performs continuous on-line
wraparound self-test, and provides
four error flags to the host CPU.
Inputs are provided for host CPU con-
trol of 6 bits of the RTU Status Word.
Its
small
hermetic
package,
-55°C to +125°C operating tempera-
ture range, and complete RTU opera-
tion make the BUS-65142 ideal for
most
MIL-STD-1553
applications
requiring hardware or microprocessor
subsystems.
MIL-STD-1553 DUAL REDUNDANT
REMOTE TERMINAL HYBRID
FEATURES
Complete Integrated Remote
Terminal Including:
–Dual Low-Power Transceivers
–Complete RT Protocol
Multiple Ordering Options;
+5V (Only), +5V/-15V, and +5V/-12V
Direct Interface to Systems With
No Processor
Radiation Tolerant Version
Available
Space Qualified Version Available
High Reliability Screening Available
DATA
BUS A
DATA
BUS B
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
TRANSCEIVER
ENCODER/
DECODER
BIT
PROCESSOR
PROTOCOL
SEQUENCER
AND
CONTROL
LOGIC
BUFFER
TRANSFER
CONTROLS
CURRENT
WORD
COUNTER
COMMAND
LATCH
STATUS
REGISTER
ERROR FLAGS
TIMING FLAGS
NBGT
INCMD
BITEN
STATEN
GBR
MESS ERR
RT FAIL
HS FAIL
RTADD ERR
ILL CMD (ME)
SS REQ
ADBC
RT FLAG
SS BUSY
SS FLAG
DAT/CMD
A5-A10
A0-A4
DTREQ
DTGRT
DTACK
DTSTR
R/W
DB0-DB15
BUF ENA
M
U
X
WATCHDOG
TIMEOUT
DDC CUSTOM CHIP
RT ADDRESS
+
PARITY
16 MHz CLOCK
FIGURE 1. BUS-65142 SERIES BLOCK DIAGRAM
DESCRIPTION
1988, 1999 Data Device Corporation
*(Note: BUS-65142 is NOT recommended for new design, use BU-61703/05 Simple System RT for new designs.
BU-65142 is NOT recommended for new design, consult factory or local representative for more information)
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| BUS-65143-370Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, QIP78 |
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| BUS-65143-520 | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, QIP78 |
| BUS-65143-570W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, QIP78 |
| BUS-65144-200K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, DFP82 |
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