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參數資料
| 型號： | BW2006L |
| 英文描述： | Rad-hard quad 2-input NAND gate |
| 中文描述： | BW2006L 100MHz的?500MHz的FSPLL BW2006L |數據資料 |
| 文件頁數： | 1/8頁 |
| 文件大?。?/td> | 814K |
| 代理商： | BW2006L |
The BW2006L is a Phase Locked Loop (PLL) Clock
frequency synthesizer constructed in CMOS on a single
monolithic structure.
The device's PLL macro functions provide frequency
multiplication capabilities.
The output clock frequency FOUT is related to the input
clock frequency FIN by FOUT=m*8*FIN/p*s.
BW2006L consists of a Phase/Frequency Detector
(PFD),
a charge pump,
external loop filter, and a
Voltage Controlled Oscillator(VCO), pre-divider(6bit),
main divider(6bit), post scaler(2bit) as shown in the block
diagram.
. 0.35u CMOS device technology
. Single power supply 3.3V
. Output frequency range: 100~500MHz
. Jitter
80ps
. Output Duty ratio 40% to 60%
.
Input Duty ratio 40% to 60%
.
Frequency changed by programmable dividers
.
Input frequency range: 10MHz
FIN
50MHz
.
Power Down mode
General Description
Features
PRE
PFD
Charge
Pump
VCO
POST
by S
Loop
Filter
External
VDD
VSS
VDDA
VSSA
VBB
P<5:0>
M<5:0>
S<1:0>
FIN
FILTER
FOUT
PWRDN
Figure1 . functional
blcok
diagram
1/8
MAIN
FUNCTIONAL BLOCK DIAGRAM
VSUB
100MHz~500MHz FSPLL
BW2006L
DECEMBER 1998. Ver1.0
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