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參數資料
| 型號： | BW4104X |
| 英文描述： | Rad-hard dual J-K flip flop with preset and clear |
| 中文描述： | BW4104X LVDS接收器|數據資料 |
| 文件頁數： | 1/7頁 |
| 文件大小： | 102K |
| 代理商： | BW4104X |
The BW4104X receiver converts the LVDS data
streams
back into 28bits of CMOS/TTL data. At a transmit clock
frequency of 65MHz, 24 bits of RGB data and 4bits of
LCD timing data and control data are transmitted at a
rate of 455Mbps per LVDS data channel. Using a
65MHz clock the throughput is 227Mbytes/sec. Devices
are offered with falling edge clocks for convenient
interface with a varity of graphics and LCD panel
controllers. This receiver is an ideal means to solve
EMI and cable size problems associated with wide high
speed TTL
interfaces.
General Description
Features
Block Diagram
Figure1 . LVDS Block Diagram
20 to 65MHz shift clock support
28:4 Data Channel Compression at up to
455Megabits/sec on each LVDS channel
Single 3.3V supply
Low Power CMOS Design
Power-down mode
Single pixel per clock XGA(1024x768) ready
Supports VGA,SVGA,XGA and higher
addressability
Up to 227 Megabytes/sec bandwidth
Narrow bus reduces cable size and cost
PLL requires no external components
Low profile 56 lead TSSOP package
Falling edge data strobe Receiver
For channel A
For channel B
For channel C
For channel D
PLL
outbuffer x 7
outbuffer x 7
outbuffer x 7
outbuffer x 7
LVDS input buffer
Serial/Parallel
Data transfer
RAN
RAP
RBN
RBP
RCN
RCP
RDN
RDP
RCLKN
RCLKP
PDWNN
CLKOUT
RXOUT<0:6>
RXOUT<7:13>
RXOUT<14:20>
RXOUT<21:27>
LVDS Receiver
BW4104X
DECEMBER 1998. Ver1.0
1 / 7
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