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參數資料
| 型號： | C15ABC |
| 英文描述： | LOW DROP POWER SCHOTTKY RECTIFIER |
| 中文描述： | 混合信號CMOS工藝和專門模擬 |
| 文件頁數： | 1/2頁 |
| 文件大小： | 47K |
| 代理商： | C15ABC |
1.5μ
m
Units
Metal I pitch (width/space)
1.5 / 1.5
μ
m
Metal II pitch (width/space)
2.0 / 1.8
μ
m
Poly pitch (width/space)
1.5 / 1.5
μ
m
Contact
1.5 x 1.5
μ
m
Via
1.8 x 1.8
μ
m
Gate geometry
1.5
μ
m
P-well junction depth
3.0
μ
m
N+ junction depth (5V&3V / 1.2V)
0.28 / 0.20
μ
m
P+ junction depth
0.28
μ
m
Gate oxide thickness
270
Inter poly oxide thickness
480
Process parameters
1.5 MICRON - 1.2 volts
1.5 MICRON - 3 volts
1.5 MICRON - 5 volts
Units
Conditions
N Channel
min. typ. max.
P Channel
min. typ. max.
N Channel
min. typ. max.
P Channel
min. typ. max.
N Channel
min. typ. max.
P Channel
min. typ. max.
Vt (50x
1.5μ
m)
0.30 0.40 0.50 0.30 0.40 0.50 0.35 0.50 0.65 0.35 0.50 0.65 0.55 0.70 0.85 0.55 0.70 0.85
V
Saturation
Ids (50x
1.5μ
m)
260
110
280
120
196 240
78 100
μ
A/
μ
m
Vds=Vgs=5V
Gain
β
(50x
1.5μ
m)
2.92
1.05
3.50
1.05
2.90
0.80
mA/V
2
Linear (1.2V&3.0V)
Saturation (5V)
Body Factor (50x50
μ
m)
0.50
0.77
0.52
0.75
0.45
0.81
√
v
Bvdss (50x
1.5μ
m)
5
10
5
9
7
12
7
12
10
12
10
12
V
Ids=20nA
Subthreshold Slope
85
105
87
106
93
101
mV/dec.
Vds=0.1V
Substrate Current
1.1
NA
0.26
NA
0.21
NA
μ
A/
μ
m
Vds=5.5V, Vgs=2.3V
Field Threshold
10
15
10
14
10
15
10
14
10
17
10
20
V
Ids = 1
μ
A/square
L Effective
1.27
1.12
1.09
1.05
1.2
1.2
μ
m
Ldrawn =
1.5μ
m
Gate Propagation Delay
Propagation Delay Time per Stage
(47 Stage Ring Oscillator)
Typ. = 2.4 ns @1.2V
Typ. = 530 ps @3.3V
Typ. = 380 ps @5.0V
P 6.3/1.5
N 2.3/1.5
Description
The 1.5μm process provides the flexibility, speed and packing density needed
in mixed signal designs. The aggressive design rules make it comparable to
most 1.2 μm processes. 3 volts and a 1.2 volts options are also available for low
voltage applications; they offer low and matched threshold voltages for
improved dynamic range.
Technology outline
Drain Engineered Structure to Ensure Reliability against Hot-Carrier Injection
Planarization with SOG Sandwich Structure
Nitride Passivation for Reliability against Moisture
Latchup Free Process on Non-Epi Material Achieved with Optimized I/O Protection
MOSFET Electrical Parameters
1.5 Micron CMOS Process Family
Features
LO
V
MOS Processes (2.7~3.6 Volts Low Voltage Option)
1.2 Volts Very Low Voltage Option
5.5 Volts Maximum Operating Voltage
Double Poly / Double Metal
3 μm Poly and Metal I Pitch
ProToDuction
TM
Option for low cost prototypes
150mm Wafers
For More Information:
DALSA Semiconductor Sales
18 Boulevard de l’Aéroport
Bromont, Québec, Canada
J2L 1S7
Tel :
(450) 534-2321 ext. 1448
(800) 718-9701
(450) 534-3201
email: dalsasales@dalsasemi.com
Fax
www.dalsasemi.com
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