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參數(shù)資料
| 型號： | C9531 |
| 廠商： | Cypress Semiconductor Corp. |
| 英文描述： | SMD LED Lamps |
| 中文描述： | PCIX I / O系統(tǒng)時鐘發(fā)生器與EMI控制功能 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 176K |
| 代理商： | C9531 |
PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07034 Rev. **
05/02/2001
Page 1 of 14
APPROVED PRODUCT
C9531
Product Features
Dedicated clock buffer power pins for reduced
noise, crosstalk and jitter
Buffer XIN Reference clock output
Input clock frequency 33.3 MHz
Output frequencies of 33.3, 66.6, 100 and 133.3
MHz selectable (PCIX requirements)
One output bank of 5 clocks.
SMBus clock control interface for individual clock
disabling and SSCG control
Output clock duty cycle is 50% (± 5%)
<250 pS skew between output clocks within a
bank
Output jitter <175 pSec.
Spread Spectrum feature for reduced EMI
OE pins for entire output bank enable control and
testability
28 Pin SSOP and TSSOP package
Block Diagram
Test Mode Logic Table
INPUT PINS
OE
S1
HIGH
LOW
HIGH
LOW
HIGH
HIGH
HIGH
HIGH
LOW
X
Note
: XIN is the frequency of the clock on the
device’s XIN pin.
OUTPUT PINS
CLK(0:4)
XIN
2 * XIN
3 * XIN
4 * XIN
Tri-State
S0
REF
XIN
XIN
XIN
XIN
Tri-State
LOW
HIGH
LOW
HIGH
X
Pin Configuration
XIN
CLK3
CLK4
OE
GOOD#
CLK2
CLK1
CLK0
/N
SSCG#
SSCG
Logic
1
0
XOUT
I
2
C
Control
Logic
SCLK
IA(0:2)
S(0,1)
SDATA
REF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD
XOUT
VSS
S1
GOOD#
VSS
IA1
IA2
AVDD
OE
IA0
SSCG#
VSS
CLK4
AVDD
CLK3
VSS
VDDP
CLK2
CLK1
CLK0
VDDP
VSS
SCLK
SDATA
C
REF
S0
XIN
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