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參數(shù)資料
| 型號(hào)： | CA3306CE |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | 6-Bit, 15 MSPS, Flash A/D Converters |
| 中文描述： | 1-CH 6-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDIP18 |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 111K |
| 代理商： | CA3306CE |
4-8
CA3306, CA3306A,
CA3306C
6-Bit, 15 MSPS,
Flash A/D Converters
August 1997
File Number
3102.1
Features
CMOS Low Power with Video Speed (Typ) . . . . .70mW
Parallel Conversion Technique
Signal Power Supply Voltage . . . . . . . . . . . . 3V to 7.5V
15MHz Sampling Rate with Single 5V Supply
6-Bit Latched Three-State Output with Overflow Bit
Pin-for-Pin Retrofit for the CA3300
Applications
TV Video Digitizing
Ultrasound Signature Analysis
Transient Signal Analysis
High Energy Physics Research
High Speed Oscilloscope Storage/Display
General Purpose Hybrid ADCs
Optical Character Recognition
Radar Pulse Analysis
Motion Signature Analysis
Robot Vision
Description
The CA3306 family are CMOS parallel (FLASH) analog-to-digital
converters designed for applications demanding both low power
consumption and high speed digitization. Digitizing at 15MHz, for
example, requires only about 50mW.
The CA3306 family operates over a wide, full scale signal input volt-
age range of 1V up to the supply voltage. Power consumption is as
low as 15mW, depending upon the clock frequency selected. The
CA3306 types may be directly retrofitted into CA3300 sockets, offer-
ing improved linearity at a lower reference voltage and high operat-
ing speed with a 5V supply.
The intrinsic high conversion rate makes the CA3306 types ideally
suited for digitizing high speed signals. The overflow bit makes pos-
sible the connection of two or more CA3306s in series to increase
the resolution of the conversion system. A series connection of two
CA3306s may be used to produce a 7-bit high speed converter.
Operation of two CA3306s in parallel doubles the conversion speed
(i.e., increases the sampling rate from 15MHz to 30MHz).
Sixty-four paralleled auto balanced comparators measure the input
voltage with respect to a known reference to produce the parallel bit
outputs in the CA3306. Sixty-three comparators are required to
quantize all input voltage levels in this 6-bit converter, and the addi-
tional comparator is required for the overflow bit.
Ordering Information
Pinouts
PART NUMBER LINEARITY (INL, DNL)
SAMPLING RATE
TEMP. RANGE (
o
C)
PACKAGE
PKG. NO.
CA3306E
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
±
0.5 LSB
15MHz (67ns)
-40 to 85
18 Ld PDIP
E18.3
CA3306CE
10MHz (100ns)
-40 to 85
18 Ld PDIP
E18.3
CA3306M
15MHz (67ns)
-40 to 85
20 Ld SOIC
M20.3
CA3306CM
10MHz (100ns)
-40 to 85
20 Ld SOIC
M20.3
CA3306D
15MHz (67ns)
-55 to 125
18 Ld SBDIP
D18.3
CA3306CD
10MHz (100ns)
-55 to 125
18 Ld SBDIP
D18.3
CA3306J3
15MHz (67ns)
-55 to 125
20 Ld CLCC
J20.B
CA3306J3
10MHz (100ns)
-55 to 125
20 Ld CLCC
J20.B
CA3306 (PDIP, SBDIP)
TOP VIEW
CA3306 (SOIC)
TOP VIEW
CA3306 (CLCC)
TOP VIEW
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
(MSB) B6
OVERFLOW
V
SS
V
Z
CE2
CLK
CE2
PHASE
V
REF
+
B5
REF
CENTER
B3
B2
B4
B1 (LSB)
V
DD
V
IN
V
REF
-
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
(MSB) B6
OVERFLOW
V
SS
NC
V
Z
CE2
CLK
CE1
PHASE
V
REF
+
B5
REF
CENTER
B3
B2
B4
B1 (LSB)
V
DD
NC
V
IN
V
REF
-
4
5
6
7
8
9 10 11 12 13
C
3
2
1 20 19
15
14
18
17
16
V
SS
V
Z
NC
CE2
CE1
REF
CENTER
B3
B1 (LSB)
V
DD
B2
B
B
N
V
R
+
V
R
-
P
V
I
B
O
F
(
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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