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參數(shù)資料
| 型號： | CAT1320YI-28TE13 |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | LEAD AND HALOGEN FREE, MO-153-AA, TSSOP-8 |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 147K |
| 代理商： | CAT1320YI-28TE13 |
12
CAT1320, CAT1321
Advance Information
Doc. No. 25085, Rev. 00
Figure 11. Selective Read Timing
*=Don’t Care Bit
Immediate/Current Address Read
The CAT1320 and CAT1321 address counter contains
the address of the last byte accessed, incremented by
one. In other words, if the last READ or WRITE access
was to address N, the READ immediately following
would access data from address N+1. For all devices,
N=E=4,095. The counter will wrap around to Zero and
continue to clock out valid data. After the CAT1320 and
CAT1321 receives its slave address information (with
the R/
W bit set to one), it issues an acknowledge, then
transmits the 8-bit byte requested. The master device
does not send an acknowledge, but will generate a
STOP condition.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condition,
slave address and byte addresses of the location it
wishes to read. After the CAT1320 and CAT1321
acknowledges, the Master device sends the START
condition and the slave address again, this time with the
R/
W bit set to one. The CAT1320 and CAT1321 then
responds with its acknowledge and sends the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1320 and CAT1321 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1320 and CAT1321 will continue to output
an 8-bit byte for each acknowledge, thus sending the
STOP condition.
The data being transmitted from the CAT1320 and
CAT1321 is sent sequentially with the data from address
N followed by data from address N+1. The READ
operation address counter increments all of the CAT1320
and CAT1321 address bits so that the entire memory
array can be read during one operation.
BUS ACTIVITY:
MASTER
SDA LINE
DATA n+x
DATA n
A
C
K
A
C
K
DATA n+1
A
C
K
S
T
O
P
N
O
A
C
K
DATA n+2
A
C
K
P
SLAVE
ADDRESS
Figure 12. Sequential Read Timing
A15–A8
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
S
T
A
R
T
A7–A0
BYTE ADDRESS
SLAVE
ADDRESS
S
A
C
K
N
O
A
C
K
S
T
A
R
T
DATA
P
S
T
O
P
****
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