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參數資料
| 型號： | CB35000 |
| 廠商： | 意法半導體 |
| 英文描述： | HCMOS STANDARD CELLS |
| 中文描述： | HCMOS標準單元 |
| 文件頁數： | 1/16頁 |
| 文件大小： | 166K |
| 代理商： | CB35000 |
CB35000 SERIES
HCMOS STANDARD CELLS
PRELIMINARY DATA
July 1995
1/16
FEATURES
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0.5 micron triple layer metal HCMOS5S pro-
cess featuring retrograde well technology,
low resistance salicided active areas, polysi-
licide gates and thin metal oxide.
3.3 V optimized transistor with 5 V I/O inter-
face capability
2 - input NAND delay of 210 ps (typ) with
fanout = 2.
Broad I/O functionality including LVCMOS,
LVTTL, GTL, PECL, and LVDS.
High drive I/O; capability of sinking up to 48
mA with slew rate control, current spike sup-
pression and impedance matching.
Generators to support SPRAM, DPRAM,
ROM and MULT with BIST options.
Extensive embedded function library includ-
ing DSP and ST micros, popular third party
micros and Synopsys synthetic libraries.
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Table 1
Module Generator Library
Cell
Description
SPRAM
256K bits max
16K word max 64 bit max
Zero static current
Tristate outputs
DPRAM
128K bits max
8K word max 64 bit max
Zero static current
Tristate outputs
ROM
2M bits max
32K word max 64 bit max
Diffusion programmable
Tristate outputs
MULT
Parallel asynchronous operation
2’s complement product
6 to 64 bits for both inputs
Ripple Carry or Fast Carry Look Ahead
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Fully independent power and ground config-
urations for inputs, core and outputs.
I/O ring capability up to 800 pads.
Output buffers capable of driving ISA, EISA,
PCI, MCA, and SCSI interface levels.
Active pull up and pull down devices.
Buskeeper I/O functions.
Oscillators for wide frequency spectrum.
Broad range of 300 SSI cells.
Low Power / Low Drive library subset.
Design For Test includes IEEE 1149.1 JTAG
Boundary Scan architecture built in.
Cadence and Mentor based design system
with interfaces from multiple workstations.
Broad ceramic and plastic package range.
Latchup trigger current > +/- 500 mA.
ESD protection > +/- 4000 volts.
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