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CB65000 Series
March 2002
FEATURE
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0.18micron drawn, six layers of metal connected
by fully stackable vias and contacts, Shallow
Trench Isolation, low resistance, salicided
active areas and gates. Deep UV lithography.
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1.8 V optimized High Performance and Low
Leakage transistors with 3.3 V I/O and supply
interface capability.
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Average gate density: 85K/mm
2
, plus low power
consumption of 30nanoWatt/Gate/MHz/
Stdload.
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Two input NAND delay of 35ps with High
Performane transistor and 60ps with Low
Leakage transistor.
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Library available in commercial, industrial and
military temperature range. Power supply
ranging from 1.2V and 1.95V for Core
(according to JESD 8-7 specification) and
between 3.0V and 3.6V for I/Os (alligned with
JESD 8-A specification).
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Broad I/O functionality including:
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Low Voltage CMOS.
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Low Voltage TTL,HSTL, SSTL.
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AGP 2X and 4X, USB, PCI, LVDS I/O interfaces
are also available.
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Drive capability up to 8 mA per buffer with slew
rate control, current spike suppression
impedance matching, and process
compensation capability to reduce delay
variation.
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Designs easily portable from previous
generations of CB55000 with an average factor
2 density increase, 30% speed improvement
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and 2.5 power reduction at respective nominal
voltages.
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Generators to support Single Port, Dual port
and multiple Port RAM, and ROMs with BIST
options.
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Extensive embedded function library including
ST DSP and micro-cores, third-party IPs,
Synopsys and Mentor Inventra synthetic
libraries ideally suited for complete System On
Chip fast integration .
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Embedded DRAM Capability
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80
μ
m pitch linear and 50
μ
m staggered pad
libraries.
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Fully independent power and ground
configuration for core and I/Os supported.
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I/O ring capability up to 1500 pads.
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Latch-up trigger current > ± 500 mA. ESD
protection above 4 kV in H.B.M.
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Oscillators and PLLs for wide frequency
spectrum.
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Broad range of more than 600 SSI cells.
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Design for test features including IEEE 1149.1
JTAG Boundary Scan architecture.
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Synopsys, Cadence and Mentor based design
systems with interface from multiple
workstations.
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Broad range of packaging solutions, including
PBGA, LBGA, SBGA, HPBGA, TQFP, PQFP,
PLCC up to 1000 pins with enhanced power
dissipation options.
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1.25 GigaHertzGigabit DLL technique.
CB65000 Super Integration
Cost Effective Product
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Architecture partitioning
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Trouble-free integration
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Application-specific
Your Product is Unique
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User specified cell integration
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Design confidentiality
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IP fully re-usable
HCMOS8D 0.18
μ
m Standard Cells Family