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參數(shù)資料
| 型號： | CD-700-KAC-NFB-12.000 |
| 英文描述： | Virtex-5 Multi-Platform FPGAs, Package: 1FF665C |
| 中文描述： | 鎖相環(huán) |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 141K |
| 代理商： | CD-700-KAC-NFB-12.000 |
Vectron International 166 Glover Avenue, Norwalk CT 06856-5160
Tel:1-88-VECTRON-1
e-mail: vectron@vectron.com
CD-700
Complete VCXO based Phase Lock Loop
Figure 1, CD-700 block diagram
Features
5 x 7.5 x 2 mm, smallest VCXO PLL available
Output Frequencies to 65.536MHz
5.0 or 3.3 Vdc operation
Tri-State Output
Loss of Signal Alarm
VCXO with CMOS outputs
0/70 or –40/85 °C temperature range
Hermetically sealed ceramic SMD package
Applications
Frequency Translation
Clock Smoothing, Clock Switching
NRZ Clock recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
Low jitter PLL’s
Description
The VI CD-700 is a user-configurable crystal
based PLL integrated circuit. It includes a digital
phase detector, op-amp, VCXO and additional
integrated functions for use in digital
synchronization applications. Loop filter software
is available as well SPICE models for circuit
simulation.
DATAIN
(5)
CLKIN
(6)
VDD
(14)
HIZ
(12)
GND
(7)
OUT2
(11)
RCLK
(9)
RDATA
(10)
OPP
(15)
LOS
(8)
PHO
(3)
OPN
(2)
OPOUT
(1)
VC
(16)
LOSIN
(4)
OP-Amp
VCXO
OUT1
(13)
Optional
2N Divider
Phase
Detector
and LOS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD-700-KAC-NFB-12.288 | Virtex-5 Multi-Platform FPGAs, Package: 1FF1136C |
| CD-700-KAC-NFB-12.352 | Platform Flash XL High-Density Configuration and Storage Device, Package: FT64C |
| CD-700-KAC-NFB-13.000 | Phase-Locked Loop |
| CD-700-KAC-NFB-16.000 | Phase-Locked Loop |
| CD-700-KAC-NFB-16.384 | Phase-Locked Loop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD-700-KAC-NFB-13.000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Phase-Locked Loop |
| CD-700-KAC-NFB-16.000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Phase-Locked Loop |
| CD-700-KAC-NFB-16.384 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Phase-Locked Loop |
| CD-700-KAC-NFB-19.440 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Phase-Locked Loop |
| CD-700-KAC-NFB-20.000 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Phase-Locked Loop |
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