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參數(shù)資料
| 型號： | CD-700-LAF-GDB-38.880 |
| 英文描述： | Phase-Locked Loop |
| 中文描述： | 鎖相環(huán) |
| 文件頁數(shù)： | 1/14頁 |
| 文件大?。?/td> | 141K |
| 代理商： | CD-700-LAF-GDB-38.880 |
Vectron International 166 Glover Avenue, Norwalk CT 06856-5160
Tel:1-88-VECTRON-1
e-mail: vectron@vectron.com
CD-700
Complete VCXO based Phase Lock Loop
Figure 1, CD-700 block diagram
Features
5 x 7.5 x 2 mm, smallest VCXO PLL available
Output Frequencies to 65.536MHz
5.0 or 3.3 Vdc operation
Tri-State Output
Loss of Signal Alarm
VCXO with CMOS outputs
0/70 or –40/85 °C temperature range
Hermetically sealed ceramic SMD package
Applications
Frequency Translation
Clock Smoothing, Clock Switching
NRZ Clock recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
Low jitter PLL’s
Description
The VI CD-700 is a user-configurable crystal
based PLL integrated circuit. It includes a digital
phase detector, op-amp, VCXO and additional
integrated functions for use in digital
synchronization applications. Loop filter software
is available as well SPICE models for circuit
simulation.
DATAIN
(5)
CLKIN
(6)
VDD
(14)
HIZ
(12)
GND
(7)
OUT2
(11)
RCLK
(9)
RDATA
(10)
OPP
(15)
LOS
(8)
PHO
(3)
OPN
(2)
OPOUT
(1)
VC
(16)
LOSIN
(4)
OP-Amp
VCXO
OUT1
(13)
Optional
2N Divider
Phase
Detector
and LOS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CD-700-LAF-GDB-39.3216 | Phase-Locked Loop |
| CD-700-LAF-GDB-40.000 | Phase-Locked Loop |
| CD-700-LAF-GDB-40.960 | Phase-Locked Loop |
| CD-700-LAF-GDB-44.736 | ATHLON 64 3600+ |
| CD-700-LAF-GDB-49.152 | ATHLON 64 4200+ |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD-700-LAF-HAD-50M0000000 | 功能描述:VCXO振蕩器 5.0V 100ppm APR -40C +85C50MHz RoHS:否 制造商:Fox 封裝 / 箱體:5 mm x 3.2 mm 頻率:19.2 Mhz 頻率穩(wěn)定性:2.5 PPM 輸出格式: 封裝:Reel 電源電壓:3 V 端接類型:SMD/SMT 尺寸:3.2 mm W x 5 mm L x 1.5 mm H 最小工作溫度:- 20 C 最大工作溫度:+ 75 C |
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| CD70-14AFTPM-Q | 制造商:Panduit Corp 功能描述: |
| CD-70-14-PY | 制造商:Thomas & Betts 功能描述: |
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