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參數資料
| 型號： | CD-700-LAF-HDB-13.000 |
| 廠商： | VECTRON INTERNATIONAL |
| 元件分類： | XO, clock |
| 英文描述： | PHASE LOCKED LOOP, CQCC16 |
| 封裝： | 5 X 7.50 MM, 2 MM HEIGHT, HERMETIC SEALED, CERAMIC, SMD-16 |
| 文件頁數： | 1/14頁 |
| 文件大小： | 123K |
| 代理商： | CD-700-LAF-HDB-13.000 |
Vectron International, 267 Lowell Rd, Hudson NH 03051-4916
Tel: 1-88-VECTRON-1
Web: www.vectron.com
Page 1 of 14
Rev : 06Apr08
CD-700
Complete VCXO Based Phase Lock Loop
Figure 1. CD-700 Block Diagram
Features
5 x 7.5 x 2 mm, smallest VCXO PLL available
Output Frequencies to 77.76 MHz
5.0 or 3.3 Vdc operation
Tri-State Output
Holdover on Loss of Signal Alarm
VCXO with CMOS outputs
0/70 or –40/85 °C temperature range
Hermetically sealed ceramic SMD package
Product is compliant to RoHS directive
Applications
Frequency Translation
Clock Smoothing, Clock Switching
NRZ Clock recovery
DSLAM, ADM, ATM, Aggregation, Optical
Switching/Routing, Base Station
Synchronous Ethernet
Low jitter PLL’s
Description
The VI CD-700 is a user-configurable crystal
based PLL integrated circuit. It includes a digital
phase detector, op-amp, VCXO and additional
integrated functions for use in digital
synchronization applications. Loop filter software
is available as well SPICE models for circuit
simulation.
DATAIN
(5)
CLKIN
(6)
VDD
(14)
HIZ
(12)
GND
(7)
OUT2
(11)
RCLK
(9)
RDATA
(10)
OPP
(15)
LO
S
PHO
(3)
OPN
(2)
OPOUT
(1)
VC
(16)
LOSIN
(4)
OP-Amp
VCXO
OUT1
(13)
Optional
2
n Divider
Phase
Detector
and LOS
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