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參數(shù)資料
| 型號(hào)： | CD40108BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs 48-SSOP -40 to 85 |
| 中文描述： | 的CMOS 4 × 4多端口注冊 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 157K |
| 代理商： | CD40108BMS |
7-25
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD40108BMS
CMOS 4 x 4 Multiport Register
Description
The CD40108BMS is a 4 x 4 multiport register containing
four 4-bit registers, write address decoder, two separate
read address decoders, and two 3-state output buses.
When the ENABLE input is low, the corresponding output
bus is switched, independently of the clock, to a high-imped-
ance state. The high-impedance third state provides the out-
puts with the capability of being connected to the bus lines in
a bus-organized system without the need for interface or
pull-up components.
When the WRITE ENABLE input is high, all data input lines
are latched on the positive transition of the CLOCK and the
data is entered into the word selected by the write address
lines. When WRITE ENABLE is low, the CLOCK is inhibited
and no new data is entered. In either case, the contents of
any word may be accessed via the read address lines inde-
pendent of the state of the CLOCK input.
The CD40108BMS is supplied in these 24-lead outline pack-
ages:
Applications
Scratch-Pad Memories
Arithmetic Units
Data Storage
Braze Seal DIP
Ceramic Flatpack
H4V
H4P
Features
High Voltage Type (20V Rating)
Four 4-Bit Registers
One Input and Two Output Buses
Unlimited Expansion in Bit and Word Directions
Data Lines have latched Inputs
3-State Outputs
Separate Control of Each Bus, Allowing Simultaneous
Independent Reading of Any of Four Registers on Bus
A and Bus B and Independent Writing Into Any of the
Four Registers
CD40108BMS is Pin-Compatible with Industry Type
MC14580
Standardized Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
5V, 10V and 15V Parametric Ratings
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
December 1992
File Number
3356
Pinout
CD40108BMS
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
Q3 B
Q2 B
3-STATE A
Q0 A
Q1 A
Q2 A
Q3 A
WRITE 0
WRITE 1
READ 1B
READ 0B
VSS
16
17
18
19
20
21
22
23
24
15
14
13
VDD
Q0 B
3-STATE B
D0
D1
D3
WRITE ENABLE
READ 1A
READ 0A
Q1 B
D2
CLOCK
Functional Diagram
20
19
18
17
8
9
14
13
10
11
D0
D1
D2
D3
WRITE 0
WRITE 1
READ 1A
READ 0A
READ 1B
23
22
7
6
5
4
2
1
Q0
Q2
Q3
Q1
READ 0B
Q0
Q2
Q3
Q1
3-STATE A
3
15
WRITE
ENABLE
21
16
CLOCK
3-STATE B
VDD = 24
VSS = 12
DATA
INPUTS
WORD A
OUTPUT
WORD B
OUTPUT
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD40109 | 制造商:Panasonic Industrial Company 功能描述:IC |
| CD40109B | 制造商:TI 制造商全稱:Texas Instruments 功能描述:CMOS QUAD LOW-TO-HIGH VOLTAGE LEVEA SHIFTER |
| CD40109BD | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD40109BD3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CD40109BDMSR | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Translator， Other/Special/Miscellaneous |
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