
4-1
CD40160BMS, CD40161BMS, CD40162BMS,
CD40163BMS
CMOS Synchronous Programmable 4-Bit
Counters
CD40160BMS,
CD40163BMS
counters. The CLEAR function of the CD40162BMS and
CD40163BMS is synchronous and a low level at the CLEAR
input sets all four outputs low on the next positive CLOCK
edge. The CLEAR function of the CD40160BMS and
CD40161BMS is asychronous and a low level at the CLEAR
input sets all four outputs low regardless of the state of the
CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD
input disables the counter and causes the output to agree
with the setup data after the next CLOCK pulse regardless of
the conditions of the ENABLE inputs.
CD40161BMS,
are
4-bit
CD40162BMS
and
synchronous
programmable
The carry look-ahead circuitry provides for cascading counters
for n-bit synchronous applications without additional gating.
Instrumental in accomplishing this function are two count-enable
inputs and a carry output (COUT). Counting is enabled when
both PE and TE inputs are high. The TE input is fed forward to
enable COUT. This enabled output produces a positive output
pulses with a duration approximately equal to the positive portion
of the Q1 output. This positive overflow carry pulse can be used
to enable successive cascaded stages. Logic transitions at the
PE or TE inputs may occur when the clock is either high or low.
The CD40160BMS through CD40163BMS types are functionally
equivalent to and pin-compatible with the TTL counter series
74LS160 through 74LS163 respectively.
The
CD40163BMS are supplied in these 16 lead outline packages:
CD40160 CD40161 CD40162 CD40163
Braze Seal DIP
H4W
Frit Seal DIP
H1F
Ceramic Flatpack
H6P
CD40160BMS,
CD40161BMS,
CD40162BMS
and
Features
High-Voltage Types (20V Rating)
CD40160BMS Decade with Asynchronous Clear
CD40161BMS Binary with Asynchronous Clear
CD40162BMS Decade with Synchronous Clear
CD40163BMS Binary with Synchronous Clear
Internal Look-Ahead for Fast Counting
Carry Output for Cascading
Synchronously Programmable
Clear Asynchronous Input (CD40160BMS, CD40161BMS)
Clear Synchronous Input (CD40162BMS, CD40163BMS)
Synchronous Load Control Input
Low Power TTL Compatibility
Standardized Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
μ
A at 18V Over Full Package
Temperature Range; 100nA at 18V and +25
o
C
Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
5V, 10V and 15V Parametric Ratings
Meets All Requirements of JEDEC Tentative Standard No. 13B,
“Standard Specifications for Description of ‘B’ Series CMOS
Devices”
Applications
Programmable Binary and Decade Counting
Counter Control/Timers
Frequency Dividing
Pinout
CD40160BMS, CD40161BMS, CD40162BMS, CD40163BMS
TOP VIEW
Functional Diagram
H4X
H1F
H6W
H4X
H1L
H6P
H4W
H1F
H6W
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
CLEAR
CLOCK
P1
P2
P3
P4
VSS
PE
VDD
Q1
Q2
Q3
Q4
TE
LOAD
CARRY OUT
7
6
10
1
9
2
3
4
5
LOAD
CLOCK
P1
P2
P3
P4
VSS = 8
TE
CLEAR
PE
Q1
Q2
Q3
Q4
CARRY
OUT
14
13
12
11
15
VDD = 16
December 1992
File Number
3358
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999