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參數(shù)資料
| 型號： | CD4018BMS |
| 廠商： | Intersil Corporation |
| 元件分類： | 通用總線功能 |
| 英文描述： | CMOS Presettable Divide-By- “N” Counter |
| 中文描述： | 的CMOS可預(yù)置分頻器的“N”反 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 85K |
| 代理商： | CD4018BMS |
7-350
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4018BMS
CMOS Presettable
Divide-By- “N” Counter
Description
CD4018BMS types consist of 5 Johnson-Counter stages,
buffered Q outputs from each stage, and counter preset con-
trol gating. CLOCK, RESET, DATA, PRESET ENABLE, and
5 individual JAM inputs are provided. Divide by 10, 8, 6, 4, or
2 counter configurations can be implemented by feeding the
Q5, Q4, Q3, Q2, Q1 signals, respectively, back to the DATA
input. Divide-by-9, 7, 5, or 3 counter configurations can be
implemented by the use of a CD4011B to gate the feedback
connection to the DATA input. Divide-by functions greater
than 10 can be achieved by use of multiple CD4018BMS
units. The counter is advanced one count at the positive
clock-signal transition. Schmitt Trigger action on the clock
line permits unlimited clock rise and fall times. A high
RESET signal clears the counter to an all-zero condition. A
high PRESET-ENABLE signal allows information on the JAM
inputs to preset the counter. Anti-lock gating is provided to
assure the proper counting sequence.
The CD4018BMS is supplied in these 16-lead outline pack-
ages:
Functional Diagram
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4T
H1F
H6W
9
7
12
3
2
16
“1”
“2”
“3”
“4”
“5”
VDD
JAM INPUTS
VSS
11
13
6
14
1
10
Q3
Q4
Q5
PRESET
ENABLE
CLOCK
DATA
B
8
15
RESET
5
4
Q2
Q1
Features
High Voltage Type (20V Rating)
Medium Speed Operation 10MHz (typ.) at VDD - VSS =
10V
Fully Static Operation
100% Tested for Quiescent Current at 20V
Standardized Symmetrical Output Characteristics
5V, 10V and 15V Parametric Ratings
Maximum Input Current of 1
μ
a at 18V Over Full Pack-
age-Temperature Range;
- 100nA at 18V and 25
o
C
Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Fixed and Programmable Divided- By-10, 9, 8, 7, 6, 5,
4, 3, 2 Counters
Fixed and Programmable Counters Greater Than 10
Programmable Decade Counters
Divide-By- “N” Counters/Frequency Synthesizers
Frequency Division
Counter Control/Timers
Pinout
CD4018BMS
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
DATA
JAM 1
JAM 2
Q2
Q1
Q3
VSS
JAM 3
VDD
CLOCK
Q5
JAM 5
Q4
PRESET ENABLE
JAM 4
RESET
November 1994
File Number
3298
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4018BMT | 功能描述:計(jì)數(shù)器 IC CMOS Presettable Divide-By-N Counter RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| CD4018BMTE4 | 功能描述:計(jì)數(shù)器 IC CMOS Presettable Divide-By-N Counter RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| CD4018BMTG4 | 功能描述:計(jì)數(shù)器 IC CMOS Presettable Divide-By-N Counter RoHS:否 制造商:NXP Semiconductors 計(jì)數(shù)器類型:Binary Counters 邏輯系列:74LV 位數(shù):10 計(jì)數(shù)法: 計(jì)數(shù)順序: 工作電源電壓:1 V to 5.5 V 工作溫度范圍:- 40 C to + 125 C 封裝 / 箱體:SOT-109 封裝:Reel |
| CD4018BMW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Johnson Counter |
| CD4018BMW/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Johnson Counter |
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