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參數(shù)資料
| 型號(hào)： | CD4042BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Quad Clocked D Latch(CMOS 四路時(shí)鐘鎖存器) |
| 中文描述： | 的CMOS四時(shí)鐘D鎖存器（的CMOS四路時(shí)鐘鎖存器） |
| 文件頁數(shù)： | 1/8頁 |
| 文件大小： | 63K |
| 代理商： | CD4042BMS |
7-868
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4042BMS
CMOS Quad Clocked “D” Latch
Pinout
CD4042BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
Q4
Q1
Q1
D1
CLOCK
POLARITY
VSS
D2
VDD
D4
D3
Q3
Q3
Q2
Q2
Q4
NC = NO CONNECTION
4
7
13
14
5
6
16
8
2
3
10
9
11
12
1
15
CL
D1
D2
D3
D4
CLOCK
POLARITY
VDD
VSS
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Features
High-Voltage Type (20V Rating)
Clock Polarity Control
Q and Q Outputs
Common Clock
Low Power TTL Compatible
Standardized Symmetrical Output Characteristics
100% Tested for Quiescent Current at 20V
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25
o
C
5V, 10V and 15V Parametric Ratings
Noise Margin (Over Full Package Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
Buffer Storage
Holding Register
General Digital Logic
Description
CD4042BMS types contain four latch circuits, each strobed by a
common clock. Complementary buffered outputs are available
from each circuit. The impedance of the n- and p- channel output
devices is balanced and all outputs are electrically identical.
Information present at the data input is transferred to outputs Q
and Q during the CLOCK level which is programmed by the
POLARITY input. For POLARITY = 0 the transfer occurs during
the 0 CLOCK level and for POLARITY = 1 the transfer occurs
during the 1 CLOCK level. The outputs follow the data input
defined above are present. When a CLOCK transition occurs
(positive for POLARITY = 0 and negative for POLARITY = 1) the
information present at the input during the CLOCK transition is
retained at the outputs until an opposite CLOCK transition
occurs.
The CD4042BMS is supplied in these 16 lead outline packages:
Braze Seal DIP
H4T
Frit Seal DIP
H1E
Ceramic Flatpack
H6W
December 1992
File Number
3310
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CD4042BNS | 制造商:Texas Instruments 功能描述: |
| CD4042BNSR | 功能描述:閉鎖 CMOS Quad Clocked ’D’ Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4042BNSRE4 | 功能描述:閉鎖 CMOS Quad Clocked ’D’ Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4042BNSRG4 | 功能描述:閉鎖 CMOS Quad Clocked ’D’ Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4042BPW | 功能描述:閉鎖 CMOS Quad Clocked ’D’ Latch RoHS:否 制造商:Micrel 電路數(shù)量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數(shù)量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時(shí)間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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