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參數資料
| 型號： | CD4099BCN |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 通用總線功能 |
| 英文描述： | 8-Bit Addressable Latch |
| 中文描述： | 4000/14000/40000 SERIES, LOW LEVEL TRIGGERED D LATCH, TRUE OUTPUT, PDIP16 |
| 封裝： | 0.300 INCH, PLASTIC, MS-001, DIP-16 |
| 文件頁數： | 1/6頁 |
| 文件大小： | 136K |
| 代理商： | CD4099BCN |
TL/F/5984
C
February 1988
CD4099BM/CD4099BC 8-Bit Addressable Latch
General Description
The CD4099B is an 8-bit addressable latch with three ad-
dress inputs (A0–A2), an active low enable input (E), active
high clear input (CL), a data input (D), and eight outputs
(Q0–Q7).
Data is entered into a particular bit in the latch when that bit
is addressed by the address inputs and the enable (E) is
low. Data entry is inhibited when enable (E) is high.
When clear (CL) and enable (E) are high, all outputs are low.
When clear (CL) is high and enable (E) is low, the channel
demultiplexing occurs. The bit that is addressed has an ac-
tive output which follows the data input while all unad-
dressed bits are held low. When operating in the address-
able latch mode (E
e
CL
e
low), changing more than one
bit of the address could impose a transient wrong address.
Therefore, this should only be done while in the memory
mode (E
e
high, CL
e
low).
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V
DD
(typ.)
Y
High noise immunity
Y
Low power TTL
compatibility
fan out of 2 driving 74L
or 1 driving 74LS
Y
Serial to parallel capability
Y
Storage register capability
Y
Random (addressable) data entry
Y
Active high demultiplexing capability
Y
Common active high clear
Connection Diagram
CD4099B
Dual-In-Line Package
TL/F/5984–1
Top View
Order Number CD4099B
Truth Table
Mode Selection
E
CL
Addressed
Latch
Unaddressed
Latch
Mode
L
H
L
H
L
L
H
H
Follows Data
Holds Previous Data
Follows Data
Reset to ‘‘0’’
Holds Previous Data
Holds Previous Data
Reset to ‘‘0’’
Reset to ‘‘0’’
Addressable Latch
Memory
Demultiplexer
Clear
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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