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參數資料
| 型號： | CD4508BMS |
| 廠商： | Intersil Corporation |
| 英文描述： | CMOS Dual 4-Bit Latch |
| 中文描述： | CMOS雙4位鎖存器 |
| 文件頁數： | 1/9頁 |
| 文件大?。?/td> | 85K |
| 代理商： | CD4508BMS |
7-1148
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright Intersil Corporation 1999
CD4508BMS
CMOS Dual 4-Bit Latch
Pinout
CD4508BMS
TOP VIEW
Functional Diagram
1
2
3
4
5
6
7
8
9
10
11
12
RESET A
STROBE A
OUTPUT DISABLE A
D0A
Q0A
D1A
Q1A
D2A
Q2A
D3A
Q3A
VSS
16
17
18
19
20
21
22
23
24
15
14
13
VDD
D3B
Q2B
D2B
Q1B
Q0B
OUTPUT DISABLE B
STROBE B
RESET B
Q3B
D1B
D0B
OUTPUT
DISABLE
D0A
D1A
D2A
D3A
STROBE
RESET
OUTPUT
DISABLE
D0B
D1B
D2B
D3B
STROBE
RESET
Q0A
Q1A
Q2A
Q3A
Q0B
Q1B
Q2B
Q3B
4-BIT
LATCH
3-STATE
OUTUTS
4-BIT
LATCH
3-STATE
OUTUTS
Features
High-Voltage Types (20-Volt Rating)
Two Independent 4-Bit Latches
Individual Master Reset for Each 4-Bit Latch
3-State Outputs with High-Impedance State for Bus
Line Applications
Medium-Speed Operation: tPHL = tPLH = 70nS (Typ.)
at VDD = 10V and CL = 50pF
100% Tested for Quiescent Current at 20V
5V, 10V, and 15V Parametric Ratings
Standardized, Symmetrical Output Characteristics
Maximum Input Current of 1
μ
A at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and 25
o
C
Noise Margin (Full Package-Temperature Range):
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
Meets all Requirements of JEDEC Tentative Standard
No. 13B, "Standard Specifications for Description of
‘B’ Series CMOS Devices"
Applications
Buffer Storage
Holding Registers
Data Storage and Multiplexing
Description
CD4508BMS dual 4-bit latch contains two identical 4-bit
latches with separate STROBE, RESET, and OUTPUT
DISABLE controls. With the STROBE line in the high state,
the data on the "D" inputs appear at the corresponding "Q"
outputs provided the DISABLE line is in the low state.
Changing the STROBE line to the low state locks the data
into the latch. A high on the reset line forces the outputs to a
low level regardless of the state of the STROBE input. The
outputs are forced to the high-impedance state for bus line
applications by a high level on the DISABLE input.
The CD4508BMS is supplied in these 24 lead outline
packages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4V
H1Z
H4P
December 1992
File Number
3337
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CD4508BNS | 制造商:Rochester Electronics LLC 功能描述: 制造商:Texas Instruments 功能描述: |
| CD4508BNSR | 功能描述:閉鎖 CMOS DUAL 4-BIT LATCH RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4508BNSRE4 | 功能描述:閉鎖 CMOS DUAL 4-BIT LATCH RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4508BNSRG4 | 功能描述:閉鎖 CMOS Dual 4B Latch RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
| CD4508BPW | 功能描述:閉鎖 CMOS DUAL 4-BIT LATCH RoHS:否 制造商:Micrel 電路數量:1 邏輯類型:CMOS 邏輯系列:TTL 極性:Non-Inverting 輸出線路數量:9 高電平輸出電流: 低電平輸出電流: 傳播延遲時間: 電源電壓-最大:12 V 電源電壓-最小:5 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:SOIC-16 封裝:Reel |
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