欧美成人免费电影,国产欧美一区二区三区精品酒店,精品国产a毛片,色网在线免费观看

參數(shù)資料
型號: CD54FCT533E
廠商: Texas Instruments, Inc.
英文描述: FCT Interface Logic Octal Transparent Latch, Three-State
中文描述: 福賽特接口邏輯八路透明鎖存器,三態(tài)
文件頁數(shù): 1/2頁
文件大小: 16K
代理商: CD54FCT533E
1
Data sheet acquired from Harris Semiconductor
SCHS272
Features
CD54/74FCT373, CD54/74FCT373AT - Non-Inverting
CD54/74FCT533 - Inverting
Buffered inputs
Typical Propagation Delay: 3.9ns at VCC = 5V,
TA = +25
o
C, CL = 50pF (FCT373AT)
SCR-Latchup-Resistant BiCMOS Process and Circuit
Design
FCTXXX Types - Speed of Bipolar FAST/AS/S;
FCTXXXAT Types - 30% Faster than FAST/AS/S with
Significantly Reduced Power Consumption
48mA to 32mA Output Sink Current (Commercial/
Extended Industrial)
Output Voltage Swing Limited to 3.7V at VCC = 5V
Controlled Output-Edge Rates
Input/Output Isolation to VCC
BiCMOS Technology with Low Quiescent Power
Description
The CD54/74FCT373, 373AT, and 533 octal transparent
latches use a small-geometry BiCMOS technology. The output
stage is a combination of bipolar and CMOS transistors that
limits the output-HIGH level to two diode drops below VCC. This
resultant lowering of output swing (0V to 3.7V) reduces power
bus ringing (a source of EMI) and minimizes VCC bounce and
ground bounce and their effects during simultaneous output
switching. The output configuration also enhances switching
speed and is capable of sinking 32mA to 48mA.
The CD54/74FCT373, 373AT, and 533 outputs are transpar-
ent to the inputs when the Latch Enable (LE) is HIGH. When
the Latch Enable (LE) goes LOW, the data is latched. The
Output Enable (OE) controls the three-state outputs. When
the Output Enable (OE) is HIGH, the outputs are in the high-
impedance state. The latch operation is independent of the
state of the Output Enable.
Ordering Information
Functional Diagram
PART NUMBER
TEMP. RANGE (
o
C)
PACKAGE
CD54/74FCT373E
-55 to 125, 0 to 70
20 Ld PDIP
CD54/74FCT373ATE
-55 to 125, 0 to 70
20 Ld PDIP
CD54/74FCT533E
-55 to 125, 0 to 70
20 Ld PDIP
CD54/74FCT373M
-55 to 125, 0 to 70
20 Ld SOIC
CD54/74FCT373ATM
-55 to 125, 0 to 70
20 Ld SOIC
CD54/74FCT533M
-55 to 125, 0 to 70
20 Ld SOIC
CD54/74FCT373SM
-55 to 125, 0 to 70
20 Ld SSOP
CD54/74FCT533SM
-55 to 125, 0 to 70
20 Ld SSOP
CD54FCT373H
-55 to 125
CD54FCT533H
-55 to 125
2
5
6
9
12
15
16
19
3
4
7
8
13
14
17
18
11
1
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
LE
OE
373
533
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
TRUTH TABLE
OUTPUT
ENABLE
LATCH
ENABLE
DATA
373,373AT
OUTPUT
533
OUTPUT
L
H
H
H
L
L
H
L
L
H
L
L
I
L
H
L
L
h
H
L
H
X
X
Z
Z
H = HIGH voltage level.
L = LOW voltage level.
X = Irrelevant.
Z = HIGH Impedance.
I = LOW voltage level one setup time
prior to the high-to-low latch enable
transition.
h = HIGH voltage level one setup time
prior to the high-to-low latch enable
transition.
February 1996
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
Harris Corporation 1996
File Number
2230.2
CD54/74FCT373,
CD54/74FCT373AT,
CD54/74FCT533
FCT Interface Logic
Octal Transparent Latch, Three-State
FAST is a registered trademark of Fairchild Semiconductor Corporation.
相關(guān)PDF資料
PDF描述
CD54FCT533H FCT Interface Logic Octal Transparent Latch, Three-State
CD54FCT533M FCT Interface Logic Octal Transparent Latch, Three-State
CD54FCT533SM FCT Interface Logic Octal Transparent Latch, Three-State
CD74FCT373AT FCT Interface Logic Octal Transparent Latch, Three-State
CD74FCT373ATE Micropower Voltage Reference 8-SOIC 0 to 70
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
CD54FCT541TM 制造商:Rochester Electronics LLC 功能描述:- Bulk
CD54FCT544EN 制造商:Rochester Electronics LLC 功能描述:- Bulk
CD54FCT573E 制造商:Harris Corporation 功能描述:
CD54FCT823AEN 制造商:Harris Corporation 功能描述:
CD54H4518F 制造商:Harris Corporation 功能描述:
主站蜘蛛池模板: 宣汉县| 石家庄市| 旬邑县| 眉山市| 黄平县| 西宁市| 张家口市| 张掖市| 龙里县| 鹿邑县| 巩义市| 延边| 广饶县| 嘉义市| 东方市| 阿拉善右旗| 高陵县| 盘锦市| 赤水市| 印江| 福安市| 涪陵区| 平凉市| 离岛区| 柳河县| 安图县| 融水| 运城市| 保亭| 镇康县| 南宁市| 武穴市| 漳浦县| 桃园市| 阳信县| 万荣县| 安化县| 启东市| 丁青县| 如皋市| 曲松县|