- 您現在的位置：買賣IC網 > PDF目錄379822 > CD54HC4059F3A (Texas Instruments, Inc.) High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter PDF資料下載
參數資料
| 型號： | CD54HC4059F3A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 通用總線功能 |
| 英文描述： | High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter |
| 中文描述： | 高速CMOS邏輯CMOS可編程分頻氮計數器 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 209K |
| 代理商： | CD54HC4059F3A |
1
Data sheet acquired from Harris Semiconductor
SCHS206B
Features
Synchronous Programmable
÷
N Counter N = 3 to 9999
or 15999
Presettable Down-Counter
Fully Static Operation
Mode-Select Control of Initial Decade Counting
Function (
÷
10, 8, 5, 4, 2)
Master Preset Initialization
Latchable
÷
N Output
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
Applications
Communications Digital Frequency Synthesizers;
VHF, UHF, FM, AM, etc.
Fixed or Programmable Frequency Division
“Time Out” Timer for Consumer-Application Industrial
Controls
Description
The ’HC4059 are high-speed silicon-gate devices that are
pin-compatible with the CD4059A devices of the CD4000B
series. These devices are divide-by-N down-counters that
can be programmed to divide an input frequency by any
number “N” from 3 to 15,999. The output signal is a pulse
one clock cycle wide occurring at a rate equal to the input
frequency divide by N. The down-counter is preset by means
of 16 jam inputs.
The three Mode-Select Inputs K
a
, K
b
and K
c
determine the
modulus (“divide-by” number) of the first and last counting
sections in accordance with the truth table. Every time the first
(fastest) counting section goes through one cycle, it reduces by
1 the number that has been preset (jammed) into the three
decades of the intermediate counting section an the last
counting section, which consists of flip-flops that are not
needed for opening the first counting section. For example, in
the
÷
2 mode, only one flip-flop is needed in the first counting
section. Therefore the last counting section has three flip-flops
that can be preset to a maximum count of seven with a place
value of thousands. If
÷
10 is desired for the first section, K
a
is
set “high”, K
b
“high” and K
c
“low”. Jam inputs J1, J2, J3, and J4
are used to preset the first counting section and there is no last
counting section. The intermediate counting section consists of
three cascaded BCD decade (
÷
10) counters presettable by
means of Jam Inputs J5 through J16.
The
channel separations of 10, 12.5, 20, 25 or 50 parts. These
inputs set the maximum value of N at 9999 (when the first
counting section divides by 5 or 10) or 15,999 (when the first
counting section divides by 8, 4, or 2).
Mode-Select
Inputs
permit
frequency-synthesizer
The three decades of the intermediate counter can be preset
to a binary 15 instead of a binary 9, while their place values
are still 1, 10, and 100, multiplied by the number of the
÷
N
mode. For example, in the
÷
8 mode, the number from which
counting down begins can be preset to:
3rd Decade
1500
2nd Decade
1st Decade
Last Counting Section
1000
150
15
The total of these numbers (2665) times 8 equals 12,320.
The first counting section can be preset to 7. Therefore,
21,327 is the maximum possible count in the
÷
8 mode.
The highest count of the various modes is shown in the
Extended Counter Range column. Control inputs K
b
and K
c
can be used to initiate and lock the counter in the “master
preset” state. In this condition the flip-flops in the counter are
preset in accordance with the jam inputs and the counter
remains in that state as long as K
b
and K
c
both remain low. The
counter begins to count down from the preset state when a
counting mode other than the master preset mode is selected.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD54HC4059F3A
-55 to 125
24 Ld CERDIP
CD74HC4059E
-55 to 125
24 Ld PDIP
CD74HC4059M96
-55 to 125
24 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
February 1998 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD54HC4059, CD74HC4059
High-Speed CMOS Logic
CMOS Programmable Divide-by-N Counter
[ /Title
(CD74
HC4059
)
/Sub-
ject
(High-
Speed
CMOS
Logic
CMOS
Pro-
相關PDF資料 |
PDF描述 |
|---|---|
| CD54HC405 | High-Speed CMOS Logic Analog Multiplexers/Demultiplexers |
| CD74HC4052SM | High-Speed CMOS Logic Analog Multiplexers/Demultiplexers |
| CD54HC4543 | HIGH-SPEED CMOS LOGIC(BCD-TO7 SEGMENT LATCH/DECODER/DRIVER FOR LCDS) |
| CD54HCT190 | HIGH SPEED CMOS LOGIC |
| CD74HCT190 | HIGH SPEED CMOS LOGIC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CD54HC4060F3A | 制造商:Texas Instruments 功能描述:Counter Single 14-Bit Binary UP 16-Pin CDIP Tube 制造商:Texas Instruments 功能描述:COUNTER SGL 14BIT BINARY UP 16CDIP - Rail/Tube 制造商:Texas Instruments 功能描述:5962-8768001EA,14-STAGE BIN COUNTER/OSC |
| CD54HC4066F3A | 制造商:Texas Instruments 功能描述: 制造商:Texas Instruments 功能描述:5962-8950701CA, QUAD BILATERAL SWITCH - Rail/Tube 制造商:Texas Instruments 功能描述:Analog Switch Quad SPST 14-Pin CDIP |
| CD54HC4075F3A | 制造商:Texas Instruments 功能描述:OR Gate 3-Element 3-IN CMOS 14-Pin CDIP Tube |
| CD54HC4094F/3A | 制造商:RCA 功能描述: |
| CD54HC4094F3A | 制造商:Texas Instruments 功能描述:Shift Register/Latch Single 8-Bit Serial to Serial/Parallel 16-Pin CDIP Tube 制造商:Rochester Electronics LLC 功能描述:- Bulk |
發布緊急采購，3分鐘左右您將得到回復。