
CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307B – JANUARY 2001 – REVISED MAY 2001
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
Buffered Inputs
±
24-mA Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description
The ’AC08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function
Y
A
B or Y
A
B in positive logic.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E
Tube
CD74AC08E
CD74AC08E
–40
°
C to 85
°
C
SOIC – M
Tube
CD74AC08M
AC08M
Tape and reel
CD74AC08M96
–55
°
C to 125
°
C
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
CDIP – F
Tube
CD54AC08F3A
CD54AC08F3A
FUNCTION TABLE
(each gate)
INPUTS
A
OUTPUT
Y
B
H
H
H
L
X
L
X
L
L
logic diagram, each gate (positive logic)
A
B
Y
Copyright
2001, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
CD54AC08 . . . F PACKAGE
CD74AC08 . . . E OR M PACKAGE
(TOP VIEW)