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參數資料
| 型號： | CD74FCT654M |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | FCT Interface Logic, Octal Bus Transceivers/ Registers, Open Drain (A Side), Three-State (B Side) |
| 中文描述： | 聯邦首都接口邏輯，八路總線收發器/寄存器，開漏（阿方），三態（乙方） |
| 文件頁數： | 1/9頁 |
| 文件大小： | 49K |
| 代理商： | CD74FCT654M |
8-1
Data sheet acquired from Harris Semiconductor
SCHS263
Features
Buffered Inputs
Typical Propagation Delay:
6.8ns at V
CC
= 5V, T
A
= 25
o
C, C
L
= 50pF
CD74FCT653
- Inverting
CD74FCT654
- Non-Inverting
SCR Latchup Resistant BiCMOS Process and
Circuit Design
Speed of Bipolar FAST/AS/S
64mA Output Sink Current
Output Voltage Swing Limited to 3.7V at V
CC
= 5V
Controlled Output Edge Rates
Input/Output Isolation to V
CC
BiCMOS Technology with Low Quiescent Power
Description
The CD74FCT653 and CD74FCT654 octal bus transceiv-
ers/registers use a small geometry BiCMOS technology. The
output stage is a combination of bipolar and CMOS transistors
that limits the output HIGH level to two diode drops below V
CC
.
This resultant lowering of output swing (0V to 3.7V) reduces
power bus ringing (a source of EMI) and minimizes V
CC
bounce and ground bounce and their effects during simulta-
neous
output
switching.
The
enhances switching speed and is capable of sinking 64mA.
output
configuration
also
The CD74FCT653 is an inverting type having open drains on
the A output and three state outputs on the B side. The
CD74FCT654 differs only in that it is a noninverting type. These
devices consist of bus transceiver circuits, D-Type flip-flops, and
control circuitry arranged for multiplexed transmission of data
directly from the data bus or from the internal storage registers.
Output Enables OEAB and OEBA are provided to control the
transceiver functions. SAB and SBA control pins are provided
to select whether real-time or stored data is transferred. The cir-
cuitry used for select control will eliminate the typical decoding
glitch that occurs in a multiplexer during the transition between
stored and real-time data. A LOW input level selects real-time
data and a HIGH selects stored data. The following examples
demonstrate the four fundamental bus management functions
that can be performed with the octal bus transceivers and regis-
ters.
Data on the A or B data bus, or both, can be stored in the inter-
nal D flip-flops by low to high transitions at the appropriate clock
pins (CAB or CBA) regardless of the select or enable control
pins. When SAB and SBA are in the real-time transfer mode, it
is also possible to store data without using the internal D-Type
flip-flops by simultaneously enabling OEAB and OEBA. In this
configuration, each output reinforces its input. Thus, when all
other data sources to the two sets of bus lines are at high
impedance, each set of bus lines will remain at its last state.
Pinouts
Ordering Information
PART NUMBER
TEMP.
RANGE (
o
C)
PACKAGE
PKG.
NO.
CD74FCT653EN
0 to 70
24 Ld PDIP
E24.3
CD74FCT654EN
0 to 70
24 Ld PDIP
E24.3
CD74FCT653M
0 to 70
24 Ld SOIC
M24.3
CD74FCT654M
0 to 70
24 Ld SOIC
M24.3
NOTE: When ordering the suffix M packages, use the entire part
number. Add the suffix 96 to obtain the variant in the tape and reel.
CD74FCT653
(PDIP, SOIC)
TOP VIEW
CD74FCT654
(PDIP, SOIC)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
CAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
A6
A7
GND
16
17
18
19
20
21
22
23
24
15
14
13
VCC
SBA
OEBA
B0
B1
B3
B5
B6
B7
CBA
B2
B4
1
2
3
4
5
6
7
8
9
10
11
12
CAB
SAB
OEAB
A0
A1
A2
A3
A4
A5
A6
A7
GND
16
17
18
19
20
21
22
23
24
15
14
13
VCC
SBA
OEBA
B0
B1
B3
B5
B6
B7
CBA
B2
B4
January 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST is a trademark of Fairchild Semiconductor.
Copyright
Harris Corporation 1997
CD74FCT653,
CD74FCT654
FCT Interface Logic, Octal Bus Transceivers/
Registers, Open Drain (A Side), Three-State (B Side)
NOT RECOMMENDED
Use CMOS Technology
File Number
2403.2
FOR NEW DESIGNS
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