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參數資料
| 型號： | CD74HCT356M96 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | High-Speed CMOS Logic 8-Input Multiplexer/Register, Three-State |
| 中文描述： | 高速CMOS邏輯8輸入多路復用器/多冊，三態 |
| 文件頁數： | 1/12頁 |
| 文件大小： | 235K |
| 代理商： | CD74HCT356M96 |
1
Semiconductor
Features
Edge-Triggered Data Flip-Flops
- Transparent Select Latches
Buffered Inputs
3-State Complementary Outputs
Bus Line Driving Capability
Typical Propagation Delay: V
CC
= 5V, C
L
= 15pF,
T
A
= 25
o
C
- Clock to Output = 22ns
Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
Wide Operating Temperature Range . . . -55
o
C to 125
o
C
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL
Logic ICs
4.5V to 5.5V Operation
Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
CMOS Input Compatibility, I
l
≤
1
μ
A at V
OL
, V
OH
Description
The CD74HCT356 consists of data selectors/multiplexers that
select one of eight sources. The data select bits (S0, S1, and
S2) are stored in transparent latches that are enabled by a low
latch enable input (LE).
The data is stored in edge-triggered flip-flops that are
triggered by a low-to-high clock transition.
In both types the 3-state outputs are controlled by three
output-enable inputs (OE1, OE2, and OE3).
Ordering Information
Pinout
CD74HCT356
(PDIP or SOIC)
TOP VIEW
PART NUMBER
TEMP. RANGE
(
o
C)
PACKAGE
CD74HCT356E
-55 to 125
20 Ld PDIP
CD74HCT356M96
-55 to 125
20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.
11
12
13
14
15
16
17
18
20
19
10
9
8
7
6
5
4
3
2
1
D7
D6
D5
D4
D3
D2
D0
D1
CP
GND
V
CC
Y
Y
OE3
OE2
OE1
S0
S1
S2
LE
SCLS459A - June 2001 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
2003, Texas Instruments Incorporated
CD74HCT356
High-Speed CMOS Logic
8-Input Multiplexer/Register, Three-State
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