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參數資料
| 型號： | CD82C284-12 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | XO, clock |
| 英文描述： | Clock Generator and Ready Interface for 80C286 Processors |
| 中文描述： | 25 MHz, PROC SPECIFIC CLOCK GENERATOR, CDIP18 |
| 文件頁數： | 1/11頁 |
| 文件大小： | 72K |
| 代理商： | CD82C284-12 |
1
March 1997
82C284
Clock Generator and Ready Interface
for 80C286 Processors
Features
Generates System Clock for 80C286 Processors
Generates System Reset Output from Schmitt
Trigger Input
- Improved Hysteresis
Uses Crystal or External Signal for Frequency Source
Dynamically Switchable between Two Input
Frequencies
Provides Local READY and MULTIBUS
READY
Synchronization
Static CMOS Technology
Single +5V Power Supply
Available in 18 Lead CerDIP Package
Description
The Intersil 82C284 is a clock generator/driver which
provides clock signals for 80C286 processors and support
components. It also contains logic to supply READY to the
CPU from either asynchronous or synchronous sources and
synchronous RESET from an asynchronous input with
hysteresis.
Pinout
82C284 (CERDIP)
TOP VIEW
Functional Diagram
Ordering Information
PART NUMBER
TEMP. RANGE
PACKAGE
PKG.
NO.
CD82C284-12
0
o
C to +70
o
C
18 Ld CERDIP F18.3
ID82C284-10
-40
o
C to +85
o
C
18 Ld CERDIP F18.3
ID82C284-12
-40
o
C to +85
o
C
18 Ld CERDIP F18.3
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1
VCC
S1
S0
NC
PCLK
RESET
RES
ARDYEN
CLK
ARDY
SRDY
SRDYEN
READY
EFI
F/C
X2
X1
GND
RESET
SYNCHRONIZER
RES
X1
X2
EFI
F/C
ARDYEN
ARDY
SRDYEN
SRDY
S1
S0
RESET
CLK
READY
PCLK
XTAL
OSC
MUX
SYNCHRONIZER
READY LOGIC
PCLK GENERATOR
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
MULTIBUS
is a patented Intel bus.
File Number
2966.1
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