- 您現在的位置：買賣IC網 > PDF目錄384185 > CDC930DL CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC PDF資料下載
參數資料
| 型號： | CDC930DL |
| 英文描述： | CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC |
| 中文描述： | CPU系統時鐘發生器| SSOP封裝| 56PIN |塑料 |
| 文件頁數： | 1/17頁 |
| 文件大小： | 240K |
| 代理商： | CDC930DL |
CDC930
133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS
WITH 3-STATE OUTPUTS
SCAS641 – JULY 2000
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Generates Clocks for Pentium
4
Microprocessors
Uses a 14.318 MHz Crystal Input to
Generate Multiple Output Frequencies
Includes Spread Spectrum Clocking (SSC),
0.6% Downspread for Reduced EMI With
Theoretical EMI Damping of 7 dB
Power Management Control Terminals
Low Output Skew and Jitter for Clock
Distribution
Operates From Single 3.3-V Supply
Consumes Less Than 30-mA Power-Down
Current
Generates the Following Clocks:
– 4 HCLK (Host) (Different Pairs–
100/133 MHz)
– 1 3VMREF Pair (3.3 V, 180
°
Shifted
50/66 MHz)
– 10 PCI (3.3 V, 33.3 MHz)
– 2 REF (3.3 V, 14.318 MHz)
– 4 3V66 MHz (3.3 V, 66 MHz)
– 2 3V48 MHz (3.3 V, 48 MHz)
Packaged in 56-Pin SSOP Package
description
The CDC930 is a differential clock synthesizer/
driver that generates HCLK/HCLK, 3VMREF/
3VMREF, PCI, 3V66, 3V48, REF system clock
signals to support a computer system with a
Pentium
4
microprocessor
Rambus
memory subsystem.
and
a
Direct
All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided
at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies
and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external
components. The host, PCI clock and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable
clock operation. All outputs have 3-state capability, which can be selected using control inputs SEL133, SelA
and SelB.
The outputs are either differential host clock or 3.3-V single-ended CMOS buffers. When PWRDWN is set to
high, the device operates in normal mode. When PWRDWN is set low, the device transitions to a power-down
mode in which HCLK is driven at 2
×
I
REF
, HCLK is not driven, and all others are set low.
Copyright
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
This is system design dependant.
Intel and Pentium
4 are trademarks of Intel Corporation.
Rambus is a trademark of Rambus Corporation.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
REF0/MultSel0
REF1/MultSel1
V
DD
3.3V
XIN
XOUT
GND
PCI0
PCI1
V
DD
3.3V
PCI2
PCI3
GND
PCI4
PCI5
V
DD
3.3V
PCI6
PCI7
GND
PCI8
PCI9
V
DD
3.3V
SEL100/133
GND
3V48(0)/SelA
3V48(1)/SelB
V
DD
3.3V
PWRDWN
V
DD
3.3V
3VMREF
3VMREF
GND
SPREAD
HCLK(1)
HCLK(1)
V
DD
3.3V
HCLK(2)
HCLK(2)
GND
HCLK(3)
HCLK(3)
V
DD
3.3V
HCLK(4)
HCLK(4)
GND
I_REF
V
DD
3.3V
GND
V
DD
3.3V
3V66(0)
3V66(1)
GND
GND
3V66(2)
3V66(3)
V
DD
3.3V
DL PACKAGE
(TOP VIEW)
相關PDF資料 |
PDF描述 |
|---|---|
| CDD1933 | TRANSISTOR | BJT | DARLINGTON | NPN | 80V V(BR)CEO | 4A I(C) | SOT-32 |
| CDD2061D | TRANSISTOR | BJT | NPN | 60V V(BR)CEO | 3A I(C) | TO-220AB |
| CDD2061E | TRANSISTOR | BJT | NPN | 60V V(BR)CEO | 3A I(C) | TO-220AB |
| CDD2061F | TRANSISTOR | BJT | NPN | 60V V(BR)CEO | 3A I(C) | TO-220AB |
| CDD2061G | TRANSISTOR | BJT | NPN | 60V V(BR)CEO | 3A I(C) | TO-220AB |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CDC930DLG4 | 功能描述:鎖相環 - PLL 133-MHz Clock Synth/ Drvr RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| CDC930DLR | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| CDC950 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:133-MHz DIFFERENTIAL CLOCK SYNTHESIZER/DRIVER FOR PC MOTHERBOARDS/SERVERS |
| CDC950DGG | 功能描述:時鐘合成器/抖動清除器 133MHz Clk Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| CDC950DGGG4 | 功能描述:時鐘合成器/抖動清除器 133MHz Clk Synth RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
發布緊急采購，3分鐘左右您將得到回復。