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參數資料
| 型號： | CDCVF857GQL |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2.5-V PHASE-LOCK LOOP CLOCK DRIVER |
| 中文描述： | 2.5 V的鎖相環時鐘驅動器 |
| 文件頁數： | 1/19頁 |
| 文件大小： | 475K |
| 代理商： | CDCVF857GQL |
SCAS047D MARCH 2003 REVISED JUNE 2005
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Recommended Applications:
DDR Memory Modules
(DDR400/333/266/200)
Zero Delay Fan-Out Buffer
Spread Spectrum Clock Compatible
Operating Frequency: 60 MHz to 220 MHz
Low Jitter (Cycle-Cycle):
±
35 ps
Low Static Phase Offset:
±
50 ps
Low Jitter (Period):
±
30 ps
1-To-10 Differential Clock Distribution
(SSTL2)
Best in Class for V
OX
= V
DD
/2
±
0.1 V
Operates From Dual 2.6-V or 2.5-V Supplies
Available in a 40-Pin MLF Package, 48-Pin
TSSOP Package, 56-Ball MicroStar Junior
BGA Package
Consumes < 100-
μ
A Quiescent Current
External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
Meets/Exceeds JEDEC Standard
(JESD821) For DDRI-200/266/333
Specification
Meets/Exceeds Proposed DDRI-400
Specification (JESD821A)
Enters Low-Power Mode When No CLK
Input Signal Is Applied or PWRDWN Is Low
description
The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock
input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback
clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback
clocks (FBIN, FBIN), and the analog power input (AV
DD
). When PWRDWN is high, the outputs switch in phase
and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state)
and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input
frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input
frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this
detection circuit turns the PLL on and enables the outputs.
When AV
DD
is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF857 is also able
to track spread spectrum clocking for reduced EMI.
Because the CDCVF857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the
PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both commercial
and industrial temperature ranges.
AVAILABLE OPTIONS
TA
TSSOP (DGG)
40-Pin MLF
56-Ball BGA
40
°
C to 85
°
C
CDCVF857DGG
(Pb-Free)
CDCVF857RTB
CDCVF857GQL
40
°
C to 85
°
C
CDCVF857RHA
(Pb-Free, Green)
Maximum load recommended is 12 pf for 200 MHz. At 12-pf load, maximum TA allowed is 70
°
C.
Copyright
2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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| CDEP104_06 | Ceramic Conformally Coated/Radial High Voltage “Gold Max"; Capacitance: 1pF; Voltage: 1000V; Tolerance: ±10%; TC: C0G; Body Size: .320" (8.13) x .280" (7.11) x .250" (6.35); Lead Style: .220" (5.59) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CDCVF857GQLR | 功能描述:時鐘驅動器及分配 2.5V Ph Lock Loop DDR Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCVF857RHA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2.5-V PHASE-LOCK LOOP CLOCK DRIVER |
| CDCVF857RHAR | 功能描述:時鐘驅動器及分配 2.5V Ph Lock Loop DDR Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCVF857RHARG4 | 功能描述:時鐘驅動器及分配 2.5V Ph Lock Loop DDR Clock Driver RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
| CDCVF857RHAT | 功能描述:時鐘驅動器及分配 2.5V Ph Lock Loop DDR Clock Dr RoHS:否 制造商:Micrel 乘法/除法因子:1:4 輸出類型:Differential 最大輸出頻率:4.2 GHz 電源電壓-最大: 電源電壓-最小:5 V 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-8 封裝:Reel |
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