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參數(shù)資料
| 型號(hào)： | CDP1823CD |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | DRAM |
| 英文描述： | 128-Word x 8-Bit LSI Static RAM |
| 中文描述： | 128 X 8 STANDARD SRAM, 450 ns, CDIP24 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 28K |
| 代理商： | CDP1823CD |
6-24
Features
Fast Access Time
- V
DD
= 5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .450ns
- V
DD
= 10V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250ns
Common Data Inputs and Outputs
Multiple Chip Select Inputs to Simplify Memory
System Expansion
Description
The CDP1823 and CDP1823C are 128-word by 8-bit CMOS
SOS static random-access memories. These memories are
compatible with general-purpose microprocessors. The two
memories are functionally identical. They differ in that the
CDP1823 has a recommended operating voltage range of
4V to 10.5V, and the CDP1823C has a recommended oper-
ating voltage range of 4V to 6.5V.
The CDP1823 memory has 8 common data input and data
output terminals for direct connection to a bidirectional data
bus and is operated from a single voltage supply. Five chip-
select inputs are provided to simplify memory-system expan-
sion. In order to enable the CDP1823, the chip-select inputs
CS2, CS3 and CS5 require a low input signal, and the chip-
select inputs CS1 and CS4 require a high input signal.
The MRD signal enables all 8 output drivers when in the low
state and should be in a high state during a write cycle.
After valid data appear at the output, the address inputs may
be changed immediately. Output data will be valid until either
the MRD signal goes high, the device is deselected, or t
AA
(access time) after address changes.
Pinout
Ordering Information
5V
10V
PACKAGE
TEMP. RANGE
PKG.
NO.
CDP1823CE
CDP1823E
PDIP
-40
o
C to +85
o
C E24.6
CDP1823CD
CDP1823D
SBDIP
-40
o
C to +85
o
C D24.6
CDP1823CDX
-
Burn-In
D24.6
CDP1823, CDP1823C
(PDIP, SBDIP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
BUS 0
BUS 1
BUS 2
BUS 3
BUS 4
BUS 5
BUS 6
BUS 7
CS1
CS2
CS3
V
SS
16
17
18
19
20
21
22
23
24
15
14
13
V
DD
MA0
MA1
MA2
MA3
MA4
MA6
MRD
CS5
CS4
MA5
MWR
March 1997
CDP1823,
CDP1823C
128-Word x 8-Bit
LSI Static RAM
File Number
1198.2
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CDP1823CDX | 128-Word x 8-Bit LSI Static RAM |
| CDP1823CE | 128-Word x 8-Bit LSI Static RAM |
| CDP1823D | 128-Word x 8-Bit LSI Static RAM |
| CDP1823E | 128-Word x 8-Bit LSI Static RAM |
| CDP1824CD3 | 8 NC Relay Outputs; For Use With:Eurotherm 6000 Series Graphical Paperless Recorders |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CDP1823CD/B | 制造商:Rochester Electronics LLC 功能描述: |
| CDP1823CD3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability CMOS 128-Word x 8-Bit Static RAM |
| CDP1823CDX | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM |
| CDP1823CE | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM |
| CDP1823D | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:128-Word x 8-Bit LSI Static RAM |
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