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參數資料
| 型號： | CDP1852 |
| 廠商： | Intersil Corporation |
| 英文描述： | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| 中文描述： | 同時，8位，模式親可編程輸入/輸出端口。（并行8位可編程模式的I / O端口） |
| 文件頁數： | 1/9頁 |
| 文件大小： | 63K |
| 代理商： | CDP1852 |
4-19
CDP1852,
CDP1852C
Byte-Wide Input/Output Port
Description
The CDP1852 and CDP1852C are parallel, 8-bit, mode-pro-
grammable input/output ports. They are compatible and will
interface directly with CDP1800-series microprocessors. They
are also useful as 8-bit address latches when used with the
CDP1800 multiplexed address bus and as I/O ports in general-
purpose applications.
The mode control is used to program the device as an input port
(mode = 0) or as an output port (mode = 1). The SR/SR output
can be used as a signal to indicate when data is ready to be
transferred. In the input mode, a peripheral device can strobe
data into the CDP1852, and microprocessor can read that data
by device selection. In the output mode, a microprocessor
strobes data into the CDP1852, and handshaking is established
with a peripheral device when the CDP1852 is deselected.
In the input mode, data at the data-in terminals (DI0-DI7) is
strobed into the port’s 8-bit register by a high (1) level on the
clock line. The negative high-to-low transition of the clock
latches the data in the register and sets the service request out-
put low (SR/SR = 0). When CS1/CS1 and CS2 are high
(CS1/CS1 and CS2 = 1), the three-state output drivers are
enabled and data in the 8-bit register appear at the data-out ter-
minals (D00-D07). When either CS1/CS1 or CS2 goes low
(CS1/CS1 or CS2 = 0), the data-out terminals are three-stated
and the service request output returns high (SR/SR =1).
In the output mode, the output drivers are enabled at all times.
Data at the data-in terminals (DI0-DI7) is strobed into the 8-bit
register when CS1/CS1 is low (CS1/CS1 = 0) and CS2 and the
clock are high (1), and are present at the data-out terminals
(D00-D07). The negative high-to-low transition of the clock
latches the data in the register. The SR/SR output goes high
(SR/SR = 1) when the device is deselected (CS1/CS1 = 1 or
CS2 = 0) and returns low (SR/SR = 0) on the following trailing
edge of the clock.
Features
Static Silicon-Gate CMOS Circuitry
Parallel 8-Bit Data Register and Buffer
Handshaking Via Service Request Flip-Flop
Low Quiescent and Operating Power
Interfaces Directly with CDP1800-Series
Microprocessors
Single Voltage Supply
Full Military Temperature Range (-55
o
C to +125
o
C)
Ordering Information
PACKAGE TEMP. RANGE
-40
o
C to +85
o
C CDP1852CE CDP1852E
-40
o
C to +85
o
C CDP1852CD CDP1852D
5V
10V
PKG.
NO.
PDIP
E24.6
SBDIP
D24.6
March 1997
File Number
1166.2
Pinout
24 LEAD DIP
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
CSI/CSI
MODE
DI0
DO0
DI1
DO1
DI2
DO2
DI3
DO3
CLOCK
V
SS
16
17
18
19
20
21
22
23
24
15
14
13
V
DD
SR/SR
DI7
DO7
DI6
DO6
DO5
DO4
CLEAR
CS2
DI5
DI4
Typical CDP1802 Microprocessor System
FIGURE 1.
TPB
Q
I/O
CDP1852
N0 - N2 MRD
DMA - IN DMA - OUT
EF1 - EF4
SC0 SC1
INTERRUPT
CONTROL
CPU
CDP1802
ADDR BUS
DATA
RAM
ROM
TPA
MRD
MWR
ADDR BUS
TPA
MRD
CEO
BIDIRECTIONAL DATA BUS
C
W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
相關PDF資料 |
PDF描述 |
|---|---|
| CDP1852C | parallel, 8-bit, mode-pro-grammable input/output ports.(并行8位可編程模式I/O端口) |
| CDP1853C | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853CD3 | High-Reliability CMOS N-Bit 1 of 8 Decoder |
| CDP1853 | N-Bit 1 of 8 Decoder |
| CDP1853CD | N-Bit 1 of 8 Decoder |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CDP1852 DIE | 制造商:Harris Corporation 功能描述: |
| CDP1852/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP18523 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
| CDP1852C | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Byte-Wide Input/Output Port |
| CDP1852C/3 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:High-Reliability Byte-Wide Input/Output Port |
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