
4-76
CDP1872C,
CDP1874C, CDP1875C
High-Speed 8-Bit Input and Output Ports
Description
The CDP1872C, CDP1874C and CDP1875C devices are
high-speed 8-bit parallel input and output ports designed for
use in the CDP1800 microprocessor system and for general
use in other microprocessor systems. The CDP1872C and
CDP1874C are 8-bit input ports; the CDP1875C is an 8-bit
output port.
These devices have flexible capabilities as buffers and data
latches and are reset by CLR input when the data strobe is
not active.
The CDP1872C and CDP1874C are functionally identical
except for device selects.The CDP1872C has one active low
and one active high select; the CDP1874C has two active
high device selects. These devices also feature Three-state
outputs when deselected. Data is strobed into the register on
the leading edge of the CLOCK and latched on the trailing
edge of the CLOCK.
The CDP1875C is an output port with data latched into the
registers when the device selects are active. There are two
active high and one active low selects. The output buffers
are enabled at all times.
Features
Parallel 8-Bit Input/Output Register with Buffered Out-
puts
High-Speed Data-In to Data-Out 85ns (Max) at V
DD
= 5V
Flexible Applications In Microprocessor Systems as
Buffers and Latches
High Order Address-Latch Capability in CDP1800-
Series Microprocessor Systems
Output Sink Current = 5mA (Min) at V
DD
= 5V
Three-State Output - CDP1872C and CDP1874C
Ordering Information
PART
NUMBER
TEMP. RANGE
PACKAGE
PKG.
NO.
CDP1872CE
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
PDIP
E22.4
CDP1874CE
PDIP
E22.4
CDP1875CE
PDIP
E22.4
March 1997
File Number
1255.2
CDP1874C INPUT PORT
(PDIP)
TOP VIEW
1
11
10
9
8
7
6
5
3
2
4
22
12
13
14
15
16
17
18
19
21
20
DI0
DO0
DI1
D01
DI2
D02
D03
DI3
CLOCK
V
SS
DI7
DI6
D06
DI5
D07
D05
DI4
D04
CLR
CS2
CS1
V
DD
CDP1875C OUTPUT PORT
(PDIP)
TOP VIEW
1
11
10
9
8
7
6
5
3
2
4
22
12
13
14
15
16
17
18
19
21
20
DI0
DO0
DI1
D01
DI2
D02
D03
DI3
CS3
V
SS
DI7
DI6
D06
DI5
D07
D05
DI4
D04
CLR
CS2
CS1
V
DD
Pinouts
CDP1872C INPUT PORT
(PDIP)
TOP VIEW
1
11
10
9
8
7
6
5
3
2
4
22
12
13
14
15
16
17
18
19
21
20
DI0
DO0
DI1
D01
DI2
D02
D03
DI3
CLOCK
V
SS
DI7
DI6
D06
DI5
D07
D05
DI4
D04
CLR
CS2
CS1
V
DD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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Copyright
Intersil Corporation 1999