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參數資料
| 型號： | CDP1877E |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 中斷控制器 |
| 英文描述： | Programmable Interrupt Controller (PIC) |
| 中文描述： | CDP1800 SERIES COMPATIBLE, INTERRUPT CONTROLLER, PDIP28 |
| 文件頁數： | 1/10頁 |
| 文件大小： | 45K |
| 代理商： | CDP1877E |
4-82
CDP1877,
CDP1877C
Programmable Interrupt Controller (PIC)
Description
The CDP1877 and CDP1877C are programmable 8-level interrupt control-
lers designed for use in CDP1800 series microprocessor systems. They
provide added versatility by extending the number of permissible interrupts
from 1 to N in increments of 8.
When a high to low transition occurs on any of the PIC interrupt lines (IR0 to
IR7), it will be latched and, unless the request is masked, it will cause the
INTERRUPT line on the PIC and consequently the INTERRUPT input on
the CPU to go low.
The CPU accesses the PIC by having interrupt vector register R(1) loaded
with the memory address of the PIC. After the interrupt S3 cycle, this regis-
ter value will appear at the CPU address bus, causing the CPU to fetch an
instruction from the PIC. This fetch cycle clears the interrupt request latch
bit to accept a new high-to-low transition, and also causes the PIC to issue a
long branch instruction (CO) followed by the preprogrammed vector address
written into the PIC’s address registers, causing the CPU to branch to the
address corresponding to the highest priority active interrupt request.
If no other unmasked interrupts are pending, the INTERRUPT output of the
PIC will return high. When an interrupt is requested on a masked interrupt
line, it will be latched but it will not cause the PIC INTERRUPT output to go
low. All pending interrupts, masked and unmasked, will be indicated by a “1”
in the corresponding bit of the status register. Reading of the status register
will clear all pending interrupt request latches.
Several PICs can be cascaded together by connecting the INTERRUPT out-
put of one chip to the CASCADE input of another. Each cascaded PIC pro-
vides 8 additional interrupt levels to the system. The number of units
cascadable depends on the amount of memory space and the extent of the
address decoding in the system.
Interrupts are prioritized in descending order; IR7 has the highest and IR0
has the lowest priority.
The CDP1877 and CDP1877C are functionally identical. They differ in that
the CDP1877 has a recommended operating voltage range of 4V to 10.5V,
and the CDP1877C has a recommended operating voltage range of 4V to
6.5V.
Features
Compatible with CDP1800 Series
Programmable Long Branch Vector Address and
Vector Interval
8 Levels of Interrupt Per Chip
Easily Expandable
Latched Interrupt Requests
Hard Wired Interrupt Priorities
Memory Mapped
Multiple Chip Select Inputs to Minimize Address
Space Requirements
Ordering Information
PACKAGE
TEMP.
RANGE
5V
10V
PKG.
NO.
PDIP
-40
o
C to
+85
o
C
CDP1877CE CDP1877E E28.6
March 1997
File Number
1319.2
Pinout
CDP1877, CDP1877C (PDIP)
TOP VIEW
CASCADE
IR7
IR6
IR5
IR4
IR3
IR2
IR1
IR0
TPA
TPB
MWR
MRD
V
SS
V
DD
BUS 7
BUS 6
BUS 5
BUS 4
BUS 3
BUS 2
BUS 1
BUS 0
CS/Ax
CS/Ay
CS
CS
INT
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Programming Model
PROGRAMMABLE INTERRUPT CONTROLLER (PIC)
BUS 7
BUS 0
PAGE REGISTER
A12
WRITE
ONLY
A15
BUS 7
A14
A13
A11
A10
A9
A8
BUS 0
CONTROL REGISTER
B4
WRITE
ONLY
B7
B6
B5
B3
B2
B1
B0
BUS 7
BUS 0
MASK REGISTER
M4
WRITE
ONLY
M7
M6
M5
M3
M2
M1
M0
BUS 7
BUS 0
STATUS REGISTER
S4
READ
ONLY
S7
S6
S5
S3
S2
S1
S0
BUS 7
BUS 0
POLLING REGISTER
P4
READ
ONLY
P7
P6
P5
P3
P2
P1
P0
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
Intersil Corporation 1999
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