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參數資料
| 型號： | CE61E15 |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數： | 1/2頁 |
| 文件大小： | 154K |
| 代理商： | CE61E15 |
Fujitsu’s CE61 is a series of high-performance, CMOS
embedded arrays featuring full support of mixed-signal
macros, as well as diffused high-speed RAMs, ROMs and a
variety of other embedded functions. The CE61 series offers
density and performance approaching standard cells, yet
provides the time-to-market advantage of gate arrays. The
E-series is optimized for pad-limited designs, and the F-series
offers a cost-effective solution for core-limited designs. A fifth
metal layer option is also available for area bump designs,
providing over 1,000 I/O pads.
Featuring true 3.3V internal operation, with 3.3V 5V and
5V tolerant I/Os, the CE61 series features a very low-power
consumption of 0.32μW/gate/MHz. Potential applications
for the CE61 series include computing, graphics, communica-
tions, networking, wireless, and consumer designs.
Features
0.28μm L
eff
(0.35μm drawn)
Propagation delay of 85 ps
Mixed-signal macros–A/D and D/A converters
High density diffused RAMs and ROMs
Separate core and I/O supply voltages
I/Os–5V 3.3V and 5V tolerant
70μm staggered pad pitch for pad-limited designs
High performance and special I/Os–311 PCML,
250 MHz LVDS, PCI, SSTL
Analog and digital PLLs
Packaging options–QFP, HQFP, BGA
Support for major third-party EDA tools
M
E-series, 70μm Staggered Pad Pitch
Optimized for Pad-Limited Designs
Total Gates
1,584K
1,149K
784K
602K
403K
280K
193K
120K
80K
64K
F-series, Optimized for Core-Limited Designs
Total Gates
2,026K
1,508K
1,182K
913K
664K
476K
303K
132K
Frame
CE61E71
CE61E59
CE61E45
CE61E35
CE61E25
CE61E19
CE61E15
CE61E09
CE61E08
CE61E07
Total Pads
672
576
480
424
352
304
256
208
176
160
Frame
CE61F80
CE61F70
CE61F60
CE61F50
CE61F40
CE61F30
CE61F20
CE61F10
Total Pads
456
400
400
352
304
256
208
144
Embedded
Hard
Macro
SoFixed
SoFixed
Clock Tree
Clk
5V I/O
5V I/O
5V I/O
5V I/O
5V I/O
3V I/O
3V I/O
3V I/O
PCML
3V I/O
3V I/O
5V I/O
5V I/O
5V I/O
5V I/O
5V I/O
CE61 Series Embedded Array
0.28μm L
eff
Description
M
相關PDF資料 |
PDF描述 |
|---|---|
| CE61E19 | FPGA |
| CE61E25 | FPGA |
| CE61E35 | FPGA |
| CE61E45 | FPGA |
| CE61E59 | FPGA |
相關代理商/技術參數 |
參數描述 |
|---|---|
| CE6206 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述: |
| CE62U | 制造商:ADAM-TECH 制造商全稱:Adam Technologies, Inc. 功能描述:CARD EDGE CONNECTORS .100 X .200 [2.54 X 5.08] CENTERLINE |
| CE-62-U | 功能描述:標準卡緣連接器 62P CARD EDGE VERT. MOUNT RoHS:否 制造商:3M Electronic Solutions Division 系列:SPD08 產品類型:Contacts 位置/觸點數量:60 安裝角:Straight 電路板厚度: 安裝風格:SMD/SMT 節距:8 mm 外殼材料:Liquid Crystal Polymer (LCP) 觸點材料:Copper Alloy 觸點電鍍:Gold |
| CE-62-U-SP1 | 制造商:Adam Technologies Inc 功能描述:62 Position 2.54mm Vertical Mount Card Edge Connector |
| CE6313 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:DVB-S Satellite Demodulator |
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