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參數(shù)資料
| 型號： | CGS702V |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI |
| 中文描述： | 702 SERIES, PLL BASED CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大小： | 181K |
| 代理商： | CGS702V |
TL/F/12386
C
September 1995
CGS702V
Commercial Low Skew PLL 1 to 9 CMOS Clock Driver
with Improved EMI
General Description
The CGS702 is an off-the-shelf clock driver specifically de-
signed for today’s high speed processors. It provides low
skew outputs which are produced at different frequencies
from three fixed input references. The CGS702 is a reduced
EMI version of the CGS700. The XTALIN input pin is de-
signed to be driven from three distinct crystal oscillators run-
ning at 25 MHz, 33 MHz or 40 MHz.
The PLL, using a charge pump and an internal loop filter,
multiplies this input frequency to create a maximum output
frequency of four times the input.
The device includes a TRI-STATE
é
control pin to disable
the outputs while the PLL is still in lock. This function allows
testing the board without having to wait to acquire the lock
once the testing is complete.
(Continued)
Features
Y
Reduced EMI compared to CGS700 (refer to EMI
characteristics)
Y
Guaranteed and tested: 500 ps pin-to-pin skew (T
OSHL
and T
OSLH
) on 1x outputs
Y
Pentium
TM
and PowerPC
TM
compatible
Y
Output buffer of nine drivers for large fanout
Y
25 MHz–160 MHz output frequency range
Y
Outputs operating at 4x, 2x, 1x of the reference
frequency for multi-frequency bus applications
Y
Selectable output frequency
Y
Internal loop filter to reduce noise and jitter
Y
Separate Analog and digital V
CC
and Ground pins
Y
Low frequency test mode by disabling the PLL
Y
Implemented on National’s Core CMOS process
Y
Symmetric output current drive:
a
30 mA/
b
30 mA I
OL
/I
OH
Y
28-pin PCC for optimum skew performance
Y
Guaranteed 2 kV ESD protection
Connection Diagram
Pin Assignment for PLCC
TL/F/12386–1
TRI-STATE
é
is a registered trademark of National Semiconductor Corporation.
Pentium
TM
is a trademark of Intel Corporation.
PowerPC
TM
is a trademark of International Business Machines Corporation.
Pin Description
PLCC Package
Pin
Name
Description
1
V
CC
Digital V
CC
2
SKWSEL
Skew Test Selector Pin
3
CLK4
4x Clock Output
4
V
CC
Digital V
CC
5
XTALIN
Crystal Oscillator Input
6
GND
Digital Ground
7
CLK1D0
V
CC
1x Clock Output
8
Digital V
CC
9
CLK1D1
GND
1x Clock Output
10
Digital Ground
11
CLK1D2
TRI-STATE
1x Clock Output
12
Output TRI-STATE Control
13
SKWTST
Skew Testing Pin
14
CLK1D3
GND
1x Clock Output
15
Digital Ground
16
CLK1D4
V
CC
1x Clock Output
17
Digital V
CC
18
EXTCLK
External Test Clock
19
GNDA
Analog Ground
20
V
CCA
Analog V
CC
21
EXTSEL
External Clock MUX Selector
22
GND
Digital Ground
23
CLK1D5
V
CC
1x Clock Output
24
Digital V
CC
25
CLK1D6
CLK1SEL
1x Clock Output
26
CLK1 Multiplier Selector
27
GND
Digital Ground
28
CLK2
2x Clock Output
C
1995 National Semiconductor Corporation
RRD-B30M105/Printed in U. S. A.
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