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參數資料
| 型號： | CH7203-V |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | MPEG to TV Encoder with 16-bit Input |
| 中文描述： | 電視的MPEG編碼器，16位輸入 |
| 文件頁數： | 1/15頁 |
| 文件大小： | 108K |
| 代理商： | CH7203-V |
201-0000-031 Rev 2.0, 6/2/99
1
CH7203
CHRONTEL
MPEG to TV Encoder with 16-bit Input
Features
Outputs to NTSC, PAL (B, D, G, H, I) and PAL-60
16-bit YCrCb (4:2:2) input format
Simultaneous composite/S-video outputs
Triple 9-bit video DACs
27 MHz DAC operating frequency eliminates
the need for 1/sinc(x) correction filter
Low-jitter phase-locked loop circuitry operates
using a low-cost 14.31818 MHz crystal
40.5 or 33.9 MHz video decoder clock output
16.934 or 11.289 MHz audio decoder clock output
13.5 MHz and 27 MHz video pixel clock outputs
Optimized luminance and chrominance internal
filters for NTSC and PAL
HSYNC* and VSYNC* outputs for
master mode operation
Sleep mode
CMOS technology in 44-pin PLCC
5V single-supply operation
Description
The CH7203 video encoder integrates a dual PLL clock
generator and a digital NTSC/PAL video encoder. By
generating all essential clock signals for MPEG
playback, and converting digital video inputs to either
NTSC or PAL video signals, the CH7203 is an essential
component of any low-cost solution for video-CD
playback machines.
The CH7203 dual PLL clock synthesizer generates all
clocks and timing signals from a 14.31818 MHz
reference crystal (see application note 19 “Tuning
Clock Outputs” for selection and tuning of the 14.31818
MHz crystal). The CH7203 generates a 40.5 or 33.9
MHz video decoder clock, 13.5 MHz and 27 MHz
video pixel clocks, and a 16.934 or 11.289 MHz audio
decoder clock. Timing signals from the PLLs are used
to generate the horizontal and vertical sync signals
which enable operating the CH7203 in master mode.
The fully digital video encoder is pin-programmable to
generate either a 525-line NTSC or a 625-line PAL
compatible video signal. It also features a logic
selectable sleep mode which turns the encoder off while
leaving both PLL’s running.
Figure 1: Functional Block Diagram
U
FILTER
V
FILTER
DAC
DAC
DAC
Σ
Σ
X
M
U
X
M
U
X
M
U
X
Y
FILTER
B LA NKIN G
COLO R-B URST
CO NTRO L
BLAN KING
H ,V SYNC
GEN ERATO R
X
SIN + COSINE
GENERATOR
ACLK
PCLK
2XPCLK
DCLK
Y
CVBS
C
Y[7:0],
C[7:0]
IREF
RSET
AVDD
VDD
AGND
GND
XI
XO/FIN
MOD0
MOD1
FS
LINEAR
INTERPOLATO R
INTERFACE
PLL1
STATE
MACHINE
OSC
PLL2
HSYNC*
VSYNC*
16
9
9
9
CRS
CRSEN*
1/2
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