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參數(shù)資料
| 型號： | CL-PD6722-V |
| 廠商： | CIRRUS LOGIC INC |
| 元件分類： | 總線控制器 |
| 英文描述： | PCMCIA BUS CONTROLLER, PQFP208 |
| 封裝： | VQFP-208 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大小： | 101K |
| 代理商： | CL-PD6722-V |
CL-PD6710/ PD6722
Preliminary Product Bulletin
May 1997
ISA (AT)
BUS
PCMCIA SOCKET 1
CL-PD6710
144-Pin VQFP
or
CL-PD6722
208-Pin PQFP and VQFP
PCMCIA SOCKET 2
(CL-PD6722)
.................
PCCr
.................
PCCr
OVERVIEW
FEATURES
I
Single-chip PCMCIA host adapters
I
Direct connection to ISA (PC AT) bus
I
Direct connection to PCMCIA socket
I
Compliant with PCMCIA 2.1 and JEIDA 4.1
I
82365SL-compatible register set,
ExCA
-compatible
I
Automatic Low-power Dynamic mode for lowest
power consumption
I
Programmable Suspend mode
I
Five programmable memory windows per socket
I
Two programmable I/O windows per socket
I
Programmable card access cycle timing
I
8- or 16-bit CPU interface
I
8- or 16-bit PCMCIA interface support
I
ATA disk interface support
I
DMA support (CL-PD6722)
I
Easy host interface using ISA I/O addresses
03E0h and 03E1h
I
Mixed-voltage (3.3V or 5V) operation
I
Single-socket interface: 144-pin VQFP for small-
est form factor (CL-PD6710)
I
Dual-socket interface: 208-pin PQFP and VQFP
(CL-PD6722)
The CL-PD6710 and CL-PD6722 are single-chip
PCMCIA host adapter chips capable of controlling
one (CL-PD6710) or two (CL-PD6722) PCMCIA
sockets. The chips are fully PCMCIA-2.1 and JEIDA-
4.1 compliant and are optimized for use in notebook
and handheld computers where reduced form factor
and low power consumption are critical design objec-
tives. With the CL-PD6710, a complete PCMCIA
solution with power-control logic can occupy as little
as 1.5 square inches (excluding the connector). The
CL-PD6722 enables a complete dual-socket PCM-
CIA solution with power-control logic in less than 2
square inches (excluding connectors).
The CL-PD6710 and CL-PD6722 chips employ
energy-efficient mixed-voltage technology that can
reduce system power consumption by over 50 per-
cent. The chips also provide a Suspend mode, which
stops the internal clock, and an automatic Low-power
Dynamic mode, which stops transactions on the
PCMCIA bus, stops internal clock distribution, and
turns off much of the internal circuitry.
(cont.)
PCMCIA Host Adapters
System
Block Diagram
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL50-1 | RING TERMINAL |
| CLG-1005-001010 | 5 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, IDC, SOCKET |
| CLG-1007-001010 | 7 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, IDC, SOCKET |
| CLG-1009-001010 | 9 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, IDC, SOCKET |
| CLG-1010-001010 | 10 CONTACT(S), FEMALE, TWO PART BOARD CONNECTOR, IDC, SOCKET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| CL-PD6722-VC-B | 制造商:Cirrus Logic 功能描述:ELECTRONIC COMPONENT |
| CL-PD6729-QC-C | 制造商:BASIS 功能描述: |
| CLPD6729QCE | 制造商:BASIS 功能描述: |
| CL-PD6729-QC-E | 制造商:CIRRUS LOGIC 功能描述: |
| CL-PD6730-QC-B79030-648AC | 制造商:CL 功能描述:CL-PD6730-QC-B79030- |
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