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參數(shù)資料
| 型號(hào)： | CL7128AETC100-5 |
| 英文描述： | Electrically-Erasable Complex PLD |
| 中文描述： | 電可擦除復(fù)雜可編程邏輯器件 |
| 文件頁數(shù)： | 1/14頁 |
| 文件大小： | 107K |
| 代理商： | CL7128AETC100-5 |
December 2000
Page 63
CL7128A
CL7128AE
CL7256A
CL7256AE
Useable Gates
2,500
5,000
10,000
Macrocells
128
256
512
Logic array Blocks
8
16
32
Max user I/O pins
100
164
212
Speed Grades
-4, -5, -6, -7, -10, -12
-4, -5, -6, -7, -10, -12
-6, -7, -10, -12
84-Pin PLCC
100-Pin TQFP
100-Pin BGA
144-Pin TQFP
100-Pin TQFP
100-Pin BGA
144-Pin TQFP
208-Pin PQFP
256-Pin BGA
144-Pin TQFP
208-Pin PQFP
256-Pin BGA
256-Pin FBGA
7KA tbl 01A
Packages
Feature
CL7512AE
u
Patented High Fidelity Conversion Technology
u
Link Processed Logic Device (LPLD
) technology offers
the ultimate combination of performance, flexibility, and
low cost
u
Functionally, architecturally, and electrically compatible
with industry-standard Altera
MAX
7000
u
High Density
-
2,500 Usable gates
-
128 Macrocells
-
100 Maximum user I/O pins
u
Metal link technology provides very fast, dense
interconnect routing
u
Low current consumption
u
Supports 3.3 volt operation
u
Alpha particle immune
CL 7000 Product F amily Overview
CL7128A
CL7128AE
Link Processed Logic Device Family
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| CL7128AETC100-6 | |
| CL7128AETC100-7 | Electrically-Erasable Complex PLD |
| CL7128AETC144-10 | |
| CL7128AETC144-4 | Electrically-Erasable Complex PLD |
| CL7128AETC144-5 | |
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