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參數資料
| 型號： | CLC016AJQ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 通信及網絡 |
| 英文描述： | Data Retiming PLL with Automatic Rate Selection |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數： | 1/20頁 |
| 文件大小： | 422K |
| 代理商： | CLC016AJQ |
CLC016
Data Retiming PLL with Automatic Rate Selection
General Description
National’s Comlinear CLC016 is a low-cost, monolithic, data
retiming phase-locked loop (PLL) designed for high-speed
serial clock and data recovery. The CLC016 simplifies high-
speed data recovery in multi-rate systems by incorporating
auto-rate select (ARS) circuitry on chip. This function allows
the user to configure the CLC016 to recognize up to four dif-
ferent data rates and automatically adjust to provide accu-
rate, low-jitter clock and data recovery. A single resistor is
used to set each data rate anywhere between 40 Mbps and
400 Mbps. No potentiometers, crystals, or other external ICs
are required to set the rate.
The CLC016 has output jitter of only 130 ps
at a 270 Mbps
data rate and 0.25% fractional loop bandwidth. Low phase
detector output offset and low VCO injection combine to en-
sure that the CLC016 does not generate bit errors or large
phase transients in response to extreme fluctuations in data
transition density. The result is improved performance when
handling the pathological patterns inherent in the SMPTE
259M video industry standard.
The carrier detect and output mute functions may be used
together to automatically latch the outputs when no data is
present, preventing random transitions. The external loop fil-
ter allows the user to tailor the loop response to the specific
application needs. The CLC016 will operate with either +5V
or 5.2V power supplies. The serial data inputs and outputs,
as well as the recovered clock outputs, allow single- or
differential-ECL interfacing. The logic control inputs are TTL-
compatible.
Applications
n
SMPTE 259M serial digital interfaces: NTSC/PAL, 4:2:2
component, 360 Mbps wide screen
n
Serial digital video routing and distribution
n
Clock and data recovery for high-speed data
transmission
n
Re-synchronization of serial data for SONET/SDH, ATM,
CAD networks, medical and industrial imaging
Features
n
Retimed data output
n
Recovered clock output
n
Auto and manual rate select modes
n
Four user-configurable data rates
n
No potentiometers required
n
External loop bandwidth control
n
Frequency detector for lock acquisition
n
Carrier detect output
n
Output MUTE function
n
Single supply operation: +5V or 5.2V
n
Low cost
Key Specifications
n
Low jitter: 130 ps
@
270 Mbps, 0.25% fractional loop
bandwidth (0.675 MHz)
n
High data rates: 40 Mbps 400 Mbps
n
Low supply current: 100 mA, including output biasing
n
Flexible fractional loop bandwidth: from 0.05% to 0.5%
Order Number
CLC016ACQ
CLC016AJQ
Temperature
0C to +70C
–40C to +85C
Package
PLCC V28A
PLCC V28A
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
DS100087-1
July 1998
C
1998 National Semiconductor Corporation
DS100087
www.national.com
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相關代理商/技術參數 |
參數描述 |
|---|---|
| CLC016AJQ | 制造商:Texas Instruments 功能描述:IC DATA RETIMING PLL SMD PLCC28 |
| CLC016AJQ/NOPB | 功能描述:IC DATA RETIMING PLL 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| CLC016AJQ-TR13/NOPB | 功能描述:IC DATA RETIMING PLL 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
| CLC016MTC | 制造商:Texas Instruments 功能描述:IC DATA RETIMING PLL SMD TSSOP28 |
| CLC016MTC/NOPB | 功能描述:IC DATA RETIMING PLL 28-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:- 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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