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參數資料
| 型號： | CLC030VEC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 消費家電 |
| 英文描述： | SMPTE 292M/259M Digital Video Serializer with Video and Ancilliary Data FIFOs and Integrated Cable Driver |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP64 |
| 封裝： | TQFP-64 |
| 文件頁數： | 1/29頁 |
| 文件大小： | 329K |
| 代理商： | CLC030VEC |
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CLC030
SMPTE 292M/259M Digital Video Serializer with Video
and Ancilliary Data FIFOs and Integrated Cable Driver
General Description
The CLC030 SMPTE 292M/259M Digital Video Serializer
with Ancilliary Data FIFO and Integrated Cable Driver is a
monolithic integrated circuit that encodes, serializes and
transmits bit-parallel digital video data conforming to SMPTE
125M and 267M standard definition, 10-bit wide component
video and SMPTE 260M, 274M, 295M and 296M high-
definition, 20-bit wide component video standards. The
CLC030 operates at SMPTE 259M serial data rates of
270 Mbps, 360 Mbps, the SMPTE 344M (proposed) serial
data rate of 540 Mbps; and the SMPTE 292M serial data
rates of 1483.5 and 1.485 Gbps. The serial data clock fre-
quency is internally generated and requires no external fre-
quency setting, trimming or filtering components*.
Functions performed by the CLC030 include: parallel-to-
serial data conversion, SMPTE standard data encoding,
NRZ to NRZI data format conversion, serial data clock gen-
eration and encoding with the serial data, automatic video
rate and format detection, ancilliary data packet storage,
manipulation and insertion, and serial data output driving.
The CLC030 has circuitry for automatic EDH/CRC character
and flag generation and insertion per SMPTE RP-165 (stan-
dard definition) or SMPTE 292M (high definition). Optional
LSB dithering is implemented which prevents pathological
pattern generation. Unique to the CLC030 are its video and
ancilliary data FIFOs. The video FIFO allows from 0 to 4
parallel data clock delays to be inserted in the data path for
video timing purposes. The ancilliary data port and on-chip
FIFO and control circuitry offer elegant handling and inser-
tion of ancilliary data packets and checksums in the ancilliary
data space. The CLC030 also has an exclusive built-in self-
test (BIST) and video test pattern generator (TPG) with SD
and HD component video test patterns: reference black, PLL
and EQ pathologicals and colour bars in 4:3 and 16:9 raster
formats for NTSC and PAL standards*. The colour bar pat-
terns feature optional bandwidth limiting coding in the
chroma and luma transitions.
The CLC030 has a unique multi-function I/O port which
provides access to control and configuration signals and
data. This port may be programmed to provide external
access to control functions and data for use as inputs and
outputs. This allows the designer greater flexibility in tailoring
the CLC030 to the desired application.At power-up or after a
reset command, the CLC030 is auto-configured to a default
operating condition. Separate power pins for the output
driver, PLL and the serializer improve power supply rejec-
tion, output jitter and noise performance.
The CLC030’s internal circuitry is powered from +2.5V and
the I/O circuitry from a +3.3V supply. Power dissipation is
typically 430mW at 1.485Gbps including two 75
AC-
coupled and back-matched output loads. The device is pack-
aged in a 64-pin TQFP.
Features
n
SDTV/HDTV serial digital video standard compliant
n
Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.4835Gbps
and 1.485 Gbps SDV data rates with auto-detection
n
LSB dithering option
n
No external serial data rate setting or VCO filtering
components required*
n
Fast PLL lock time:
<
150μs typical at 1.485 Gbps
n
Adjustable depth video FIFO for timing alignment
n
Built-in self-test (BIST) and video test pattern generator
(TPG)*
n
Automatic EDH/CRC word and flag generation and
insertion
n
On-chip ancilliary data FIFO and insertion control
circuitry
n
Flexible control and configuration I/O port
n
LVCMOS compatible data and control inputs and
outputs
n
75
ECL-compatible, differential, serial cable-driver
outputs
n
3.3V I/O power supply, 2.5V logic power supply
operation
n
Low power: typically 430mW
n
64-pin TQFP package
n
Commercial temperature range 0C to +70C
*
Patent applications made or pending.
Applications
n
SDTV/HDTV parallel-to-serial digital video interfaces for:
— Video cameras
— VTRs
— Telecines
— Digital video routers and switchers
— Digital video processing and editing equipment
— Video test pattern generators and digital video test
equipment
— Video signal generators
Order Number CLC030VEC
64-Pin TQFP
NS Package Number
VEC-64A
PRELIMINARY
February 2002
C
I
2002 National Semiconductor Corporation
DS200003
www.national.com
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