
N
CLC532
High-Speed 2:1 Analog Multiplexer
General Description
The CLC532 is a high-speed 2:1 multiplexer with active input and
output stages. The CLC532 also employs a closed-loop design which
dramatically improves accuracy. This monolithic device is constructed
using an advanced high-performance bipolar process.
The CLC532 has been specifically designed to provide settling times
of 17ns to 0.01%. This, coupled with the adjustable noise-bandwidth,
makes the CLC532 an ideal choice for infrared and CCD imaging
systems. Channel-to-channel isolation is better than 80dB @
10MHz. Low distortion (80dBc) and spurious signal levels make the
CLC532 a very suitable choice for both I/Q processors and receivers.
The CLC532 s offered over both the ndustrial and military temperature
ranges. The Industrial versions, CLC532AJP\AJE\AID, are specified
from -40°C to +85°C and are packaged in 14-pin plastic DIP's, 14-pin
SOIC's and 14-pin Side-Brazed packages. The extended temperature
versions, CLC532A8B/A8D/A8L-2, are specified from -55°C to +125°C
and are packaged in a 14-pin hermetic DIP and 20-terminal LCC
packages. (Contact factory for LCC and CERDIP availability.)
Ordering Information ...
CLC532AJP
CLC532AJE
CLC532ALC
CLC532AMC
CLC532A8B
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-40
o
C to +85
o
C
-55
o
C to +125
o
C
-55
o
C to +125
o
C
14-pin plastic DIP
14-pin plastic SOIC
dice
dice, MIL-STD-833
14-pin CERDIP;
MIL-STD-883
20-terminal LCC;
MIL-STD-883
CLC532A8L-2A
-55
o
C to +125
o
C
Contact factory for other packages and DESC SMD number.
June 1999
C
H
Features
I
12-bit settling (0.01%) - 17ns
I
Low noise - 32
μ
Vrms
I
High isolation - 80dB @ 10MHz
I
Low distortion - 80dBc @ 5MHz
I
Adjustable bandwidth - 190MHz (max)
Applications
I
Infrared system multiplexing
I
CCD sensor signals
I
Radar I/Q switching
I
High definition video HDTV
I
Test and calibration
Typical Application
Pinout
DIP & SOIC
20-Terminal LCC
R
L
R
IN
R
IN
IN
B
10
6
IN
A
4
3
2
1
7
V
OUT
12
CHANNEL A
CHANNEL B
CHANNEL
SELECT
C
COMP2
C
COMP1
CLC532
D
REF
11
SELECT OUTPUT
1
Channel A
0
Channel B
GND
IN
A
GND
IN
B
DGND
D
REF
SELECT
+V
CC
+V
CC
COMP
1
OUTPUT
COMP
2
V
EE
V
EE
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TOP VIEW
C
1
N
O
N
C
2
14 15 16 17 18
9
10
11
12
13
8
7
6
5
4
3
2
1
20
19
D
REF
SELECT
NC
V
EE
V
EE
D
N
I
B
N
G
IN
A
GND
NC
+V
cc
+V
cc
INDEX CORNER
1999 National Semiconductor
Corporation
Printed in the U.S.A.
http://www.national.com